Teradyne - Semiconductor Test Division

Semiconductor Test is a lead-ing supplier of semiconductor test equipment for logic, RF, analog, power, mixed-signal, and memory technologies. We deliver test solutions to developers and manufacturers of a broad range of integrated circuits, packaged separately or integrated as System-On-a-Chip (SOC) or System-In-Package (SIP) devices. ICs tested by Teradyne are used in computing, communications, consumer, automotive, identification, and internet applications.

J750Ex

Technology Overview

The J750Ex enhances Teradyne’s revolutionary J750 Family technology by providing enhanced capabilities with a higher digital data rate, increased vector memory, more power supplies for higher parallelism, better edge placement accuracy, and more scan depth.

Teradyne was the first ATE vendor to combine four channels of ATE timing functionality into a single ASIC. The J750 design team created an innovative technique to isolate the digital and analog sections of the chip and prevent interaction between channels. This enabled the integration of a full 64 channels of a VLSI test system onto a single printed circuit board.

 

ISOChannel Design

ISOChannel technology provides the foundation for putting four high-performance channels on a single chip: the QUAD C Timing Generator ASIC. With 16 QUAD C ASICs per board and 16 boards per system, the J750 platform can deliver 1024 pins in a test head only system.

 

Per-pin Test Architecture

Implemented with per-pin distributed pattern architecture, J750 systems can perform high levels of parallel test, even when testing devices requiring digital, memory, and mixed signal test. This per-pin architecture provides the ability to universally locate test options throughout the system. As a result, there are no slot boundaries, allowing for more flexibility in system configurations and maximizing test functions and pin counts.

 

OPTISite Parallel Test Technology


The J750 Platform incorporates OPTISite parallel test technology utilizing SIMULSite registers and IG-XL software to achieve high parallel test efficiency. The SIMULSite hardware registers provide simultaneous programming and failure analysis of all sites. IG-XL software is designed and optimized to streamline multisite programming and testing.


Air-cooled, “Zero footprint” System Design
     
The increased level of integration was key to eliminating the system mainframe and interconnection cabling, enabling a complete VLSI test system in an air-cooled test-head-only configuration. The J750 “zero footprint design” minimizes space requirements allowing more efficient use of production floor space and reducing the total cost of ownership.

 

 

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