Teradyne - Semiconductor Test Division

Semiconductor Test is a lead-ing supplier of semiconductor test equipment for logic, RF, analog, power, mixed-signal, and memory technologies. We deliver test solutions to developers and manufacturers of a broad range of integrated circuits, packaged separately or integrated as System-On-a-Chip (SOC) or System-In-Package (SIP) devices. ICs tested by Teradyne are used in computing, communications, consumer, automotive, identification, and internet applications.

J750

System Options: Mixed-Signal Option

Lowest Cost Test Solution for Mixed-Signal Devices

The J750 with Mixed Signal Option (MSO) provides a new approach to testing microcontroller mixed-signal devices at up to 32 sites in parallel, using an efficient, graphical programming interface.

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The J750 Mixed Signal Option consists of a Low-to-Mid Frequency (LMF) Analog Signal I/O Module (ASIO) and a companion Digital Signal I/O Module (DSIO). Both provide multiple device test channels on each module, with up to 32 instruments or sites supported in the J750 test system.

Low-to-Mid-Frequency ASIO

Each ASIO provides the following functions:

Analog sources:

  • Four (4) independent, differential, arbitrary waveform outputs
  • Per Pin Measurement Units (PPMU) for parallel parametric testing
  • Selectable source bandwidth
  • Source memory and DSP per channel

Analog capture:

  • Four (4) independent differential digitizers
  • PPMU for parallel parametric testing
  • Selectable capture bandwidth
  • Dual-ported capture memory

Per ASIO:

  • Sixteen (16) pattern-controlled relay drivers and utility bits
  • On-board 24-bit DC meter
  • On-board sequencer (one per ASIO)

Digital I/O Module

Each DSIO module aligns with a digital channel board. So, the J750 can be configured with as many DSIOs as there are digital channel boards in the system. Each DSIO module provides two digital source and two digital capture channels with the following modes of operation:

25 MHz Mode

  • Up to 32 bit serial source and serial capture
  • Up to 32 bit parallel source or parallel capture

50 MHz Mode

  • Up to 32 bit serial source and serial capture
  • Up to 16 bit parallel source or parallel capture

High-Level Test Programming Environment

Test Elements and Test Procedures represent a new test creation model, utilizing a graphical language for specifying tests at a level between the code-based model and the template-based model. Test Elements and Test Procedures provide the flexibility and power required to implement and optimize tests for mixed signal devices. Due to its graphical nature and convenience features, the Test Procedure test creation model is easy to learn and use, allowing test engineers to become more productive more quickly.