Click
here for a preview of the new and innovative solutions
that Teradyne will show at APEX 2003
The only place in North America you'll see electronics
assembly equipment from every major pick and place manufacturer
as well as exhibitors representing all other parts of
the electronics assembly supply chain.
Dates, Location and Times...
Anaheim CA
March 31 - April 2 2003
APEX 2003 Exhibit Hours
Exhibits Open:
Monday, March 31: 10a-7p
Tuesday, April 1: 10a-6p
Wednesday, April 2: 10a-3p
Visit us at Booth # 2050
What we're showing...
Optima 7210™ optical
process test (OPT) system
Innovative Machine Vision Technology Combines Exceptional
Performance And Speed
Introducing the Optima 7210™ optical process test
(OPT) system from Teradyne, representing groundbreaking
developments in PCBA vision technology, and an exciting
alternative to conventional in-process measurement and
defect detection. The Optima 7210 system features the
revolutionary VARI-Smart™ image compensation technology,
a patented image analysis and object recognition technology
capable of performing PCBA tests for placement and paste
defects in a single pass, while also providing in-line
monitoring capability for placement and paste process
conditions.
The Optima 7210 system's leading-edge technology is
a revolutionary approach to visual recognition that
combines exceptional performance and speed. Its patented
image analysis technology replaces user judgment and
skill with built-in knowledge of SMD process variation.
Images are analyzed for defects and for manufacturing
process trends that indicate future defects. The innovative
recognition technology simplifies programming and runtime,
while eliminating continuous tweaking of programs over
time. Optima 7210 programs can be written and debugged
rapidly because variation is compensated for and actively
managed, not left to lengthy program modification throughout
production.
Introducing the TestStation™
LH
Low-Cost, Fully Functional In-Circuit-Test System Features
Low-Voltage Capability
Teradyne introduces the TestStation™ LH, the most
affordable TestStation ever. The TestStation LH comes
in a in a small footprint package, is expandable up
to 4096 pins, and features the voltage accuracy and
backdrive current measurement found in UltraPin test
technology that makes it the best choice for testing
today's and tomorrow's low voltage technologies.
A cost-effective in-circuit test solution for the high-volume
consumer, computer and communications electronics market,
TestStation LH combines the renowned reliability and
performance of Teradyne's proven in-circuit test technologies,
with the convenience of a turnkey test programming environment
solution. TestStation LH is also fully compatible with
existing programs and fixtures of all GR 228X and TestStation
in-circuit test systems to preserve the investments
of current customers with new test needs.
Integrated
Test and Inspection Management for Process Optimization
Accelerated development cycles, cost reductions, shorter
product lives, and a rising demand for smaller, more complex,
portable electronics are among the critical challenges
facing today's high-volume electronics manufacturing OEMs
and contract manufacturers.
In response to these challenges, and with an eye to the
future, Teradyne has developed the D2B™ family of design-to-build
software applications to complement its innovative in-circuit,
optical machine vision, and X-Ray test and inspection
systems. Now, PCB manufacturers can utilize integrated
test strategies to optimize their manufacturing processes.
Our integrated test area will be featuring:
D2B/Strategist
Optima 7300
XStation 4010
TestStation SE
Technical Presentations:
Learn more about new advancements in the assembly test
area as Teradyne participates in three papers at this
year's show.
| Tuesday, April 1, 2003 |
1:30 PM - 3:00 PM |
|
| Session: Quality/Process
Improvement |
| Paper Title: Management
Processes for DPMO Metrics Reduce the Cost of PCB
Assembly |
| Presenter: Amit Verma |
| Manufacturers can
use DPMO metrics to reduce the cost of PCB assembly
with fewer resources. DPMO data can be used for
predicting the fault spectrum on future products,
quoting new business, setting quality targets for
manufacturing, defining test strategies, predicting
yields, or estimating shipped quality levels. Manufacturers
can input DPMO and BOM data into cost calculator
tools to estimate manufacturing costs. When combined
with a few site specific assumptions about labor
rates and test strategy, roughly 80% of PCB assembly
costs fall into place once there is a clear definition
of the DPMO. In this way, manufacturers can determine
targets for both in-process quality and financial
profit and loss. Tools are now available to the
industry that make use of DPMO data for strategic
decision making applications. Use case examples
are shown. |
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| Tuesday, April 1, 2003 |
3:15 PM – 5:15 PM |
|
| Session: Inspection
Techniques |
| Paper Title: "Biologically
Inspired Vision for PCBA Manufacturing" |
| Presenter: John Arena |
For test engineers
and managers, automated optical inspection (AOI)
systems have emerged as a countermeasure to the
growing threats of lost physical or electrical access
to assembled PCB. AOI systems are successfully employed
in high volume PCB applications to complement existing
electrical test methods with noted results of overall
better coverage, and higher yield at later test
stages. Inspection systems are commoditized, readily
available from many suppliers, and primarily evaluate
the presence of assembly defects (solder, component,
assembly), overcoming the need for physical access
that test mandates.
In the process, the limitations of optical inspection
have also become apparent. Optical inspection is
notably successful where board volume and process
stability are established. But where board volumes
are modest, or where process variation and changeovers
are common occurrence (such as in high mix environments),
or where inspection must be relied upon as the exclusive
solution, (i.e. where electrical test is not viable)
AOI exposes shortcomings to the user.
All conventional inspection systems depend in large
measure on heuristics-based (the trial and error
experimentation) data as the means to establish
typical conditions, the degree of normal variation
and the thresholds for nominal pass/fail conditions.
The use of empirical processes is a sound basis
to make decisions where the sample population being
employed is large enough to mimic the whole.
However, user assessments of heuristics put requirements
on skill and experience of programmers. As a result,
the ‘competency’ of empirical methods are built
up over time and over volume by basing ‘good’ on
historical values and historical volumes, as see
through the filter of user judgment. Where time
and volume are insufficient to establish stable
norms, or where user judgment of good and bad are
questionable, heuristic based programs are a challenge
to effectively deploy. |
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| Wednesday, April 2, 2003 |
10:45 AM – 12:15 PM |
|
| Session: Rework/Repair |
| Paper: "Flexible
Rules Based Thermal Profiling for Rework" |
| Presenter: Don Naugler |
Surface Mount Rework
systems have evolved into sophisticated thermal
processing tools with the ability to accurately
mimic original reflow oven profiles at a localized
rework site. Features such as automated profile
generation allow the user to quickly define workable
profiles for a wide variety of applications. However,
many of today’s applications demand more carefully
crafted profiles than can be achieved using traditional
methods. Sensitive components such as optical devices,
connectors, and certain package types, to name a
few, have specific requirements and limitations
that go far beyond the typical solder joint time-temperature
profile. Elevated temperatures of lead free processes
further amplify thermal management issues.
Rules Based Thermal Profiling allows automated profile
generation with a combination of parameters that
that are set to meet each situation. Multiple criteria
may be specified and prioritized to yield the most
reliable process for reworking sensitive components
and assemblies. |
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Teradyne will also be chairing the following sessions/meetings:
| Tuesday, April 1, 2003 |
9:00 am - 10:30 am |
|
| Session: Boundary
Scan |
| Chair: Michael
Smith – Teradyne, Inc. |
|
| Tuesday, April 1, 2003 |
10:45 am - 12:15 pm |
|
| Session: Inspection/Test/Repair |
| Chair: Michael
Smith – Teradyne, Inc. |
|
| Tuesday, April 1, 2003 |
3:15 pm - 5:15 pm |
|
| Meeting: NEMI Test
Strategy Open/Free Forum Presentation |
| Chair: Amit Verma
– Teradyne, Inc. |
|
| Wednesday, April 2, 2003 |
9:00 am - 10:30 am |
|
| Session: Free Forum
- Lessons Learned from IPC-2501 Test Bed Performance
Trials |
| Chair: Allan Fraser
– Teradyne, Inc. |
|
| Wednesday, April 2, 2003 |
10:45 am - 12:15 pm |
|
| Session: Factory
Information Management |
| Chair: Allan Fraser
– Teradyne, Inc. |
|
| Wednesday, April 2, 2003
|
1:30 pm - 4:30pm |
|
| Session: IPC CAMX
(254X) Committee Meeting |
| Chair: Allan Fraser
– Teradyne, Inc. |
|
| Wednesday, April 2, 2003
|
10:00 am - 12:00 pm |
|
Session: IPC subcommittee
on Automated Inspection Technologies (7-32)
Please note: The IPC 7-32
committee meeting at APEX has been moved to April
2nd 10am (from April 3rd as stated during the web
seminar) |
| Chair: Amit Verma
– Teradyne, Inc. |
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For more show information see the Apex
2003 website.
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