LASAR V6.52 Upgrade Features Ease-of-Use Enhancements

BOSTON, MA -- May 22, 1997 -- Teradyne has announced the release of an upgraded version of the LASAR V6 Digital Simulation System and a new LASAR-VT option for simulation of VHDL/VITAL models. The new LASAR V6.52 release includes many new capabilities and ease-of-use enhancements. The LASAR-VT option enables the reuse of design models for digital test development, eliminating duplicate modeling effort for ASICs and programmable devices described in VHDL/VITAL format. LASAR V6 is widely used for digital test program set (TPS) development by government agencies and military services, military contractors, and suppliers of sophisticated computer and telecommunications systems.

Reuse of VHDL/VITAL Models Speeds Test Development

The new LASAR-VT option provides a simple, automated process for converting ASIC and FPGA macrocells and device models expressed in VHDL's VITAL language from design databases into LASAR test simulation models. These models support all the features required for high-fault-coverage digital test program development and diagnostics: min/max timing and fault simulation, and backannotation of post-layout timing information expressed in Standard Delay Format (SDF), OVI 2.1. Post-layout SDF files can be supplied by any delay calculation tool, including synthesizers and layout programs.

LASAR-VT is a direct result of Teradyne's participation in the Virtual Test (VTest) project sponsored by the U.S. Air Force Wright Laboratories. One objective of this project is to develop and integrate new tools and methodologies that can be used in a "virtual test" environment that reduces TPS development time and costs by enabling the reuse of design data for test development.

VITAL (VHDL Initiative Toward ASIC Libraries, IEEE 1076.4) is a subset of the VHDL language. Since 1995, most ASIC and FPGA vendors have adopted VITAL as a modeling standard. As a result, VITAL-compliant designs have become a natural by-product of the design synthesis process. With the LASAR-VT option, synthesized ASIC and FPGA designs are now completely reusable in LASAR-eliminating the need to remodel these custom and semi-custom devices for test simulation.

According to Dave Rolince, LASAR product manager, "VHDL and VITAL are standard high-level languages for describing an electronic circuit, and they are increasingly being used by government and industry to enable interoperability between tools used for electronics design and test. These standards mean that now we can provide a simple, automated process that eliminates the need for development and maintenance of separate design and test model databases."

Noted Rolince, "Model development, by itself, can account for up to 40% of the time it takes to deliver a test program for a modern printed circuit board containing complex ASIC and FPGA devices. With the LASAR-VT option, a test developer can convert any custom or semi-custom device from VITAL to LASAR format in a matter of minutes. That's a powerful tool for accelerating the delivery of test programs and reducing costs."

LASAR-VT requires the latest release of LASAR, (Version 6.52), and the VITAL cell libraries for the device series in use (available from ASIC/FPGA suppliers). It can be purchased as an upgrade to an existing LASAR V6.52 license or with a new LASAR license. Pricing begins at $10,000.

Many New LASAR V6.52 Features Based on User Feedback

The new LASAR V6.52 release incorporates over 100 new features and improvements, many in response to user requests. Top-ranked new capabilities that enhance user efficiency include:

Network licensing. This new licensing capability allows test developers to run LASAR on any supported computer in a network-making the best use of simulation and computing resources.

Synopsys/LM model support. For users of Synopsys/LM hardware modelers, a new utility converts standard LM hardware models into LASAR-ready format in minutes, allowing LASAR users to leverage their investment in LM models for full LASAR simulation, including min/max timing analysis and fault simulation. (This new utility can be used with modular LM ModelSource 3200/3400 systems and networked LM1400 systems.)

Wire-delay analysis. A new wire-delay-analysis capability for high-speed ASICs improves the accuracy of correlation analysis, which allows LASAR to adjust its timing analysis to reflect real-life conditions. This new capability also makes it is easier to view the timing contribution of each wire delay.

PERUSE enhancements. New user selections in LASAR's PERUSE waveform display offer more flexibility for reviewing and debugging simulation results.

Postscript printing. New postscript printing capabilities allow users to customize PERUSE output files, control formatting, and output large displays on multiple pages.

LASAR V6.52 is available on workstations from Digital Equipment Corp. (Alpha OVMS 7.1 and VMS 5.5-2H4, 6.2, 7.1), Hewlett-Packard (HPUX 10.10), and Sun (Solaris 2.5, SunOS 4.1.4). Pricing for a single-user LASAR V6.52 license begins at $60,000. Customers with a current LASAR Software Support Agreement will receive the new release at no charge as part of their support agreement.

Boston-based Teradyne, Inc. is the world's largest supplier of automatic test equipment and software for the electronics and telecommunications industries, and a leading supplier of telephone line test equipment and high-performance backplane assemblies and connectors. The company's Assembly Test Division in Boston is the world's leading supplier of COTS (commercial-off-the-shelf) test equipment for defense electronics.

LASAR (Logic Automated Stimulus and Response) is a tradename of Teradyne, Inc. Other product names are trademarks of their respective owners.