ASIC Test Engineers at Teradyne participate in a self-directed, team environment with senior Test Engineers. In this role, you will develop test solutions for ASICs used to manufacture Teradyne’s testers.  Position involves designing and implementing ASIC test solutions including interface fixture designs, test program development, and device debug for digital, mixed-signal and RF devices. You will also perform failure analysis of devices to determine the root cause of failures (such as device defects, test inaccuracies, design margin limitations, correlation issues).

Daily assignments may include:

• Analysis of ASIC circuits and their specs to determine characterization methods
• Writing detail characterization plans and selecting proper lab equipment
• Design of PCB test fixtures and support circuitry for characterizing analog/digital or mixed signal ASICs
• Measurement of device parametrics using bench instrumentation and/or Automated Test Equipment
• Test programming, debug of early silicon, test time reduction and yield improvement
• Programming in Visual Basics using IEEE 488 GPIB interface to lab equipment and automate characterization procedures
• Evaluating and verifying the reliability of custom semiconductor devices
• Collecting characterization data, analyzing it and writing characterization final report
• Debug of characterization fixture (HW/SW/lab equipment)

ASIC/FPGA Verification/Design Engineers at Teradyne contribute to the architecture, design, and verification of Digital and Mixed Signal devices. You will use the latest tools and methodologies in developing these designs (Verilog HDL, System C, Cadence, SystemVerilog Assertions (SVA), Synplicity, and Hspice analog simulation, among others). Teradyne designs are implemented in the latest processes of our vendors, in 0.18 to 0.09 micron technologies. FPGA designs use the latest devices available from Altera and Xilinx.

ASIC/FPGA Design/Verification Engineers at Teradyne are involved in the design and verification of the following for a variety of end-applications, including, Digital, DC, Baseband and RF instrumentation:

• State-of-the-art FPGAs
• Gate Arrays
• Standard Cell ASICs
• Full custom ASICs combining analog and digital circuits

Assignments may include:

• Creating specifications
• Verilog coding
• Creation of testbenches in verilog, C++ and System C, SystemVerilog Assertions (SVA)
• Planning and coding of verification tests
• Timing closure and physical design
• Lab debug and design validation
• Design of FPGAs as support circuitry on characterization fixture

The development environment for Hardware Engineering includes:

• Individual project assignments
• Small group projects with other engineers
• Close interaction with SW and Hardware engineers