Process-oriented, graphical UI that systematically leads you through the steps to develop a fault coverage, diagnostic test.

Program generation debug tools that help you quickly zero in on programming errors

Automatically generates 100% pin shorts and opens fault coverage test patterns for boundary in-circuit and virtual interconnect configurations of boundary scan parts.

Automatically generates patterns and properly diagnoses faults on boundary scan devices with differential leads, and interconnect configurations with series and non-scan components.

Automatically generates a Test Access Port Integrity Test (TAPIT). A TAPIT is the first test applied and verifies the operation of basic boundary scan functions in a device prior to applying a full boundary scan test. TAPIT is also used to verify the manufacture’s ID, part number and version information stored in the devices ID register.

Outputs all board topology, scan chain, test pattern and diagnostic results in XML

Verifies a device’s adherence to IEEE 1149.1 specifications including its BSDL file.

Outputs test vectors in industry standard Serial Vector Format (SVF)

Direct post-processing to Teradyne M9-Series and Spectrum 8800 series digital channel cards.

Supported under Windows 95/98/2000/NT/XP