Hot Topics

	Hot Topics Suggested topics for TUG 2012 are listed below. However, we will accept abstracts for any topic relevant to Teradyne products and our industry. Click here to download the Hot Topics. Defense & Aerospace Program \| Semiconductor Test Program
	Defense & Aerospace Program (top) ATLAS integration Characterization of Legacy ATS for replacing instruments that do not have a compatible COTS replacement Enhancing existing tests with new instrument capabilities Mixed signal testing with the Ai-760 and the Di-Series Parallel/Operational test with the Ai-7 Series Sending and receiving data with the Di-Series Spectrum 9100-Series M9-Series to Di-Series migration System characterization for instrument replacement Techniques for new Di-Series TPS development Testing unique busses using the Bi4-Series Semiconductor Test Programs (top) Digital Concurrent Test: Using Multiple Time Domains and Protocol Aware Engines Device Jitter Measurement Techniques DIB Design Techniques for Gigabit-per-second Digital Signals Faster embedded flash memory testing High-speed Serial Interface Testing How do you Use Scan Pattern Failure Data? Highly Parallel Test New Techniques for Reducing Cost of Test Protocol Aware ATE Mixed Signal (top) Best Techniques for the DSSC - DigSrc and DigCap Concurrent Test Implementations and Tools Digital Signal Processing Algorithms and Techniques Low-leakage DIB Design Techniques Overcoming the Challenges Encountered in the Testing of MEMS Devices Parallel test efficiency Techniques for Optimizing Test Program Throughput Power Management/Automotive (top) DIB Design Techniques for Automotive Devices New Emerging Markets in Automotive SMPS Test Techniques Techniques for Optimizing Test Program Throughput Test for quality IDDQ Testing Stress Testing RF Wireless (top) Integration of ESA into test program RF wafer probe Techniques for Optimizing Test Program Throughput Testing LTE devices Testing RFIDs and NFC Devices Wafer Level Chip Scale Package Testing of RF Devices Test Infrastructure and Production (top) 3D Packaging Test Strategies Adaptive Test Flow for Improving Throughputs Benchmarking Tester Performance DUT Board Considerations for Highly Parallel Test Reduced Pin Count Test Software tools for Improved Test Development Productivity Test Program Architecture to Facilitate Code Reuse and Program Modularity Testing with Strip Handlers: Lessons Learned and Benefits Gained Yield Learning and Diagnostics
	Teradyne Users Group Conference Hilton Head, South Carolina, USA April 30 - May 2, 2012

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