High Pin Count LVTTL/LVDS I/O with FPGA Configurability

HSSub 6020Best choice when current or future requirements include:

  • High pin count LVTTL and LVDS capability
  • High throughput IEEE 1149.1 test and memory programming
  • Conventional stored pattern capability
  • FPGA configurability to address a variety of low-level bus specifications

Technical Description

  • Broad IEEE 1149.1 Boundary Scan support
    • Supported by the runtime software from the major third-party vendors
    • Conventional interconnect tests through large-capacity Flash programming
    • Multiple Test Access Ports and large pin count parallel I/O
    • Serial Vector Format (SVF) runtime capability (HSSub App included in TriFlex software)
  • Teradyne eDigital HSSub App provides conventional stored pattern (truth table) testing (included in HSSub TriFlex software)
  • Flexible low-level HSSub Tier 1 I/O Bus Processing
    • Reconfigurable HSSub Tier 1 (I/O Bus Processing) of the HSSub Three Tier Architecture implemented by a large Test Defined FPGA and local memory
    • Configured in seconds by HSSub Apps supported by Teradyne, end-users, and third-party developers
    • HSSub App development, if required, is simplified by FPGA template code based on standard design patterns
    • HSSub TriFlex Infrastructure Software interfaces provide access to the hardware from Windows Tier 3 or HSSub Tier 2 instruments

Key Attributes

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