Combined Multi-Gigabit Serial and LVDS I/O with FPGA Configurability

HSSub 6040Best choice when current or future requirements include: 

  • Flexible low-level support of bidirectional Multi-Gigabit serial ports to 5Gb/s and LVDS ports to 800Mb/s
  • FPGA configurability to address a variety of low-level bus specifications

Technical Description

  • Flexible low-level HSSub Tier 1 I/O Bus Processing
    • Reconfigurable HSSub Tier 1 (I/O Bus Processing) of the HSSub Three Tier Architecture implemented by a large Test Defined FPGA and local memory
    • Configured in seconds by HSSub Apps supported by Teradyne, end-users, and third-party developers
    • HSSub App development, if required, is simplified by FPGA template code based on standard design patterns
    • HSSub TriFlex Infrastructure Software interfaces provide access to the hardware from Windows Tier 3 or HSSub Tier 2 instruments

Key Attributes

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