Instrument Overview

  • Teradyne PXI Express HSSub instruments address the challenge of recent and upcoming test requirements including increasing speed, data volume, protocol and processing complexity, as well as low-latency UUT interaction
  • Instruments are configured and accessed via application-specific HSSub Apps that are authored by Teradyne, end users, or third-party developers
  • HSSub Instruments employ a Three-Tier architecture to perform the critical operations associated with old, new, custom, and standard digital interfaces
  • The time-critical operations take place within the instruments, independent of the central computer and Windows operating system
  • Multiple autonomous instruments, independent of central resources, support concurrent asynchronous UUT interfacesHSSub-Three-Tier-Architecture.PNG

There is a wide range of HSSub instrumentation that provide tier1, tier 2, or combined functionality.

Reconfigurable Core Instruments

  • HSSub 5010HSSub Core Instruments combine a Test Defined FPGA for low-level I/O Bus Processing (tier 1) and a multi-core processor with RTOS for Upper Level Protocol Real-Time Processing (tier 2) into a single open-architecture instrument
  • Two Core Instruments share identical internal structure:
    • The Serial Core Instrument supports up to 16 bidirectional channels at up to 3.125 Gb/s
    • The LVDS Core Instrument supports up to 72 LVDS differential pairs at up to 800 Mb/s
  • A TPS-invoked HSSub App loads processor-based procedures and Test Defined FPGA code, configuring the instrument in seconds
  • The processor and FPGA have large, high-speed local memories
  • Each instrument can run autonomously, independent of the Windows-based computer (tier 3), and multiple instruments can run concurrently
  • Direct paths between tiers 1 & 2 provide the lowest possible latency for time-critical protocols
  • For more information on Core Instruments:

Real-Time Processing Modules

  • HSSub 5020The Real-Time Processor Module provides the same multi-core processor with RTOS capability as the Core Instruments
  • The module typically provides Real-Time Processing (tier 2) support in conjunction with other  HSSub instruments handling low-level I/O Bus Processing (tier 1)
  • HSSub Apps associate the processor modules with other instruments and configures them within seconds
  • Each Real-Time Processor Module and associated instruments can run autonomously, independent of the Windows-based computer (tier 3), and multiple groups of instruments can run concurrently
  • For more information on Real-Time Processor Module:

Reconfigurable IO Expansion Instruments

  • HSSub-Reconfigurable-IO-Expansion-Instruments.pngHSSub Reconfigurable IO Expansion Instruments provide low-level I/O Bus Processing (tier 1) with large, high-performance Test Defined FPGAs
  • Reconfigurable instruments can be repurposed from one TPS to another to meet a wide range of bus requirements; standard-compliant as well as variations from standards, well-specified as well as those with evolving needs
  • A TPS-invoked HSSub App loads the Test Defined FPGA code, configuring the instrument in seconds
  • Each instrument contains large, high-speed local memory directly accessible to the FPGA
  • IO Expansion Instruments may be controlled directly by the tier 3 Windows computer for applications that do not require real-time support
  • IO Expansion Instruments may be associated with a Real-Time Processor in a Core Instrument, or a standalone Real-Time Processor Module
  • Each IO Expansion Instrument has unique capabilities to support applications with various I/O signal requirements, channel counts, and parallel or serial buses
  • For more information on Reconfigurable IO Expansion Instruments:
      LVTTL
    TTL
     LVDS  Serial
     HSSub-6020 LVTTL
     X    X  
     HSSub-6040
         X  5 Gb/s
     eDigital-6020A  X  X  X  
     eDigital-6020C  X X
     X  
     HSSub-6100 12G Serial
          12.5 Gb/s

Flexible IO Expansion Instruments

  • HSSub 9010Flexible IO Expansion Instruments share a common, high-performance FPGA-based infrastructure
  • Integrated Physical Interface Modules (PIM) provide bus-specific I/O capability
  • A TPS-invoked HSSub App loads the Test Defined FPGA code, configuring the instrument in seconds
  • Each instrument contains large, high-speed local memory directly accessible to the FPGA
  • IO Expansion Instruments may be controlled directly by the tier 3 Windows computer for applications that do not require real-time support
  • IO Expansion Instruments may be associated with a Real-Time Processor in a Core Instrument, or a standalone Real-Time Processor Module
  • Standard Teradyne-supplied HSSub Apps and utilities provide the most commonly required functionality
  • For more information on Flexible IO Expansion Instruments:
  1G Ethernet
RS232/IRIG-B
 RS485  HOTLink/ECL
Bus Controller
 Dedicated Chipset
FPGA
FPGA Dedicated HOTLink FPGA ECL
 HSSub-9030
     X  X
 HSSub-9050  X  X
 

Standard Bus Instruments

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  • The HSSub dedicated bus instruments provide the highest density and performance available in single-slot, 3U PXI Express form factor
  • The most widely used standard serial buses are best served by instruments based on bus-specific dedicated chipsets with provide a broad range of configurability that is controlled by HSSub Apps
  • HSSub-6090/6091 Ethernet instruments:
    • Support copper-based or optical Ethernet
    • Share data with Tier 2 functionality if real-time Upper Level Protocol processing is required
  • The HSSub-6120 FireWire Instrument implements the AS5643 Upper Level Protocol in an onboard Tier 2 Real-Time Processor
  • The HSSub-8030 provides common PC buses in an instrument as a more supportable approach than servicing the UUT directly from a computer
  • For more information on the Standard Bus Instruments:

Additional Instruments & Accessories

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