This FAQ answers frequently asked questions about Teradyne's native boundary scan solution, Scan Pathfinder II, which is an option on Teradyne's TestStation in-circuit test systems.

  1. What is Scan Pathfinder II?

    Scan Pathfinder II is Teradyne’s native solution for performing boundary scan testing on limited access Printed Circuit Boards. It supports testing of boundary scan components that are compliant with the specifications described in the 1149.1 and 1149.6 IEEE Boundary Scan standards.

    Teradyne native BasicSCAN and Scan Pathfinder products are the preferred boundary scan test solutions on TestStation ICT test systems. These Teradyne developed boundary scan solutions have been specifically integrated within the TestStation software and hardware to perform comprehensive boundary scan tests in the in-circuit test environment and they are tightly integrated with the in-circuit test generators; using available tester instrumentation hardware to apply the boundary scan test vectors and to increase overall test fault coverage (no external hardware is required to execute the boundary scan tests).

    To accommodate the boundary scan testing preferences of our diverse customer base, Teradyne has also formed strategic partnerships with companies who sell popular PC-based boundary scan solutions (such as Asset, Corelis, Goepel and JTAG Technologies). Teradyne’s flexible TestStation system architecture allows manufacturers to easily add these partner boundary scan hardware and software solutions to the test system when they have a need to re-use existing tests that have been developed using these solutions.

  2. What tester hardware does Scan Pathfinder II require?

    The Scan Pathfinder II solution uses the standard TestStation driver/sensor pins to drive and sense the boundary scan test access port (TAP) pins (TDI, TMS, TCK, TDO, and TRST). The boundary scan vector data is stored in TestStation’s UltraPin board pin memory.

    The nets connected to the TAP pins must be nailed and must have digital test capability (cannot be connected to an Analog Only pin board). If the application has a single scan chain, the TCK pin can optionally be connected to a tester Clock Driver nail - which will result in faster performance and reduced test vectors.

  3. What tester software does Scan Pathfinder II require?

    The Scan Pathfinder II software is available in TestStation Version 7.1 or later software releases running under the Windows 7 operating system.

  4. How is Scan Pathfinder II different from the original Scan Pathfinder?

    The original Scan Pathfinder was designed to support the boundary scan capabilities defined by IEEE Std. 1149.1. The IEEE Std. 1149.6 standard was approved in 2003 to augment the original standard and support the efficient testing of boundary scan parts that incorporate Advanced I/O features.

    Scan Pathfinder II is a new revision of software that supports both the IEEE 1149.1 and 1149.6 standards and is designed for the rapid and accurate detection and diagnosis of interconnect defects on PCB’s despite the fault-masking effects of differential signaling and the DC blocking effects of AC-coupled signals.

    Scan Pathfinder II software includes the following enhancements:

    • Support for the Windows 7 Operating System
    • Shorted Cap fault detection test for capacitors on 1149.6 nets
    • Streamlined vector generation algorithms for faster execution
    • Updated test generation user interface
    • More comprehensive diagnostic and fault coverage reports
    • New user options for controlling the test generator
      • Specification of non-test nodes
      • Ability to force node groupings for Interaction and Opens tests
      • Control option for how bidirectional pins are tested
      • New default settings that limit number of nails used per Burst
      • Automatic inclusion of ASSIGN LGC statement logic levels
    • Updated product manuals and online help

  5. What kinds of boundary scan tests does Scan Pathfinder II support?

    Scan Pathfinder II provides a suite of tests that are designed for detecting both structural and component defects on PCBs that have boundary scan components.

    • Hardware Test – This is a collection of tests that run to verify that the boundary scan Test Access Port and related test registers are functioning properly. These tests will verify that all TMS, TDI, TDO, TCK, and TRST pins are functioning, that data can be shifted through the scan path(s) and that the length of the Instruction and Boundary registers is accurate. The Hardware tests must pass before any of the other boundary scan tests will be executed.
    • IDcode / Usercode Tests - This is an optional test that checks to make sure any IDCODE and USERCODE values listed in the boundary scan device BSDL files match those of the on-board devices.
    • Interactions Tests - This is an optional test whose purpose is to detect shorts between nailed non-boundary scan nets and unnailed boundary scan nets. The test drives the nailed non-bscan nets with a pattern and verifies that they do not cause adverse interaction with the pattern being driven on the unnailed boundary scan nets. One or more Interactions tests are generated for each non-boundary scan device, but the user can control the maximum number of nails to use during Interaction test Bursts.
    • Opens Test – This is an optional test that uses the Driver/Sensor nails in the test system to detect any Opens on boundary scan pins that have test access. One or more Opens tests are generated for each boundary scan device, but the user can control the maximum number of nails to use during Opens test Bursts.
    • Interconnect Test – This is an optional test whose primary purpose is to detect Opens and Shorts between unnailed boundary scan nets. The Interconnect test includes 1149.1 and 1149.6 connections as well as single-ended and differential signals. The Interconnect test can also include nailed external boundary scan input and output nodes (those nets that have a single boundary scan input or output pin that goes off the board). The number of nailed nodes to include in the Interconnect test can be controlled by the test developer.
    • Shorted CAPs Test – This is an optional test designed to detect shorted capacitor defects between 1149.6 AC-coupled nets.
    • RUNBIST Test – This is an optional test that will execute any built-in-self test instructions associated with the boundary scan device BSDL files.

      The decision of which boundary scan tests to generate for best results is highly dependent on the PCB configuration, the available tester access and the overall manufacturing test strategy.

  6. What is the difference between Scan Pathfinder II and Teradyne's partner boundary scan product offerings?

    Scan Pathfinder is Teradyne’s limited access boundary scan test solution. It uses independent boundary scan test generation software to automatically analyze the circuit and BSDL files and determine the boundary scan parts and how they are interconnected. It then generates the appropriate Hardware, Opens, Interactions, Interconnect, and BIST tests using Teradyne’s standard software and instrumentation.

    The benefits of Teradyne’s Scan Pathfinder II native boundary scan solution include:
    • Developers and manufacturers do not need to install any additional software or hardware. Scan Pathfinder is built into Teradyne’s standard ICT development software.
    • Scan Pathfinder uses the in-circuit tester nails and bscan virtual nails in concert to maximize test coverage and repeatability.

    There are some restrictions that developers should consider before deciding to use Scan Pathfinder:
    • Scan Pathfinder tests must be developed independently and are not re-usable on other test platforms.
    • Scan Pathfinder does not support programming ISP and FLASH through the boundary scan chain (Teradyne has separate native solutions for programming FLASH and ISP components).
    • Scan Pathfinder generates canned tests for detecting typical manufacturing faults – the software does not support the generation of custom boundary scan tests or bit level manipulation of the scan vector cell data during test debug.

    TestStation’s partnership boundary scan product offerings can be integrated on Teradyne’s in-circuit testers as an option. These solutions use the partner boundary scan development software, along with a boundary scan controller and TAP module hardware that plugs into the tester PC controller or test fixture. Using these partner solutions, manufacturers can develop and debug their boundary scan tests using an offline PC. When ready, those tests can then be transported to appropriately configured Teradyne in-circuit testers.

    The benefits of using a partner boundary scan solution on your TestStation system include:
    • The boundary scan tests that are developed during the engineering and NPI phases of board introduction can be leveraged during ICT production testing (no need to re-develop boundary scan tests on the ICT). Many manufacturers are familiar with the leading PC-based boundary scan solutions and are already using them in their development labs and production facilities. Integrating these boundary scan solutions into Teradyne test equipment allows manufacturers to re-use the boundary scan tests they have already developed and thus reduce their overall in-circuit test development efforts.
    • Many partner boundary scan solutions support engineering development tools that allow generation of custom boundary scan tests and they have advanced debug tools that support bringing up boundary scan tests very quickly.
    • Partner boundary scan solutions, in addition to executing boundary scan tests, can optionally be used to program Programmable Logic Devices (PLDs) or perform Processor based functional testing.

    Keep in mind that you can install more than one boundary scan solution on the tester and decide for each application which one best suits your needs.

  7. How is Scan Pathfinder II licensed?

    Scan Pathfinder II is an optional feature available for TestStation program development and production testing environments. The three licensed components of Scan Pathfinder are:
    • Scan Pathfinder II Program Prep Single-User License – This is a program prep license for TestStation Development Pro that allows test developers to run the Scan Pathfinder test generation software to automatically generate boundary scan test programs for PCBs that utilize IEEE 1149.1 and 1149.6 compliant boundary scan components.
    • Scan Pathfinder Test and Diagnostic License – This Runtime only license enables operators to run Scan Pathfinder tests on the tester and use the Scan Pathfinder IEEE 1149.1 boundary scan diagnostic software. If the Scan Pathfinder program code includes tests for IEEE 1149.6 Advanced Digital I/O networks, then the Scan Pathfinder II Advanced Diagnostic License must also be purchased.
    • Scan Pathfinder II Advanced Diagnostic License – This Runtime only license enables operators to use the specialized Scan Pathfinder boundary scan diagnostic software required to diagnose advanced IEEE 1149.6 digital network failures.

    To enable these software licenses, end users must purchase the licenses from Teradyne (1-800-TERADYNE) and enable them the same way as other TestStation software options utilizing Teradyne’s self-service license manager client utility.

  8. How many scan paths does Scan Pathfinder support?

    Scan Pathfinder supports numerous scan path configurations which include the traditional single scan path, single paths with buffered TAP signals, multiple independent scan paths, parallel shared data paths, and hybrid path schemes.

    Basically, any configurations that are allowed by the 1149.1 standard are supported. Scan Pathfinder analyzes the circuit data and BSDL models, recognizes both simple and complex configurations and automatically generates the appropriate tests. Developers do not have to identify the scan path configurations to the test generator, it determines them automatically.

    If necessary, the Scan Pathfinder user options template provides a built-in function that can be used by developers to define the scan path configuration and override the scan path calculated by the software.

    If the application only requires a single scan path, Scan Pathfinder can use a TestStation Clock Drive nail resource to drive the TCK pin which will result in faster test execution of the boundary scan tests and reduced test vectors. For applications that require multiple scan paths, TestStation Driver/Sensor nails will be used to drive the TAP signals – the only practical limitation on the number of scan paths that can be supported is the number of real nails available in the test system.

    The data for each scan path is stored in Teradyne’s UltraPin D/S pin memory which allows storage of up to 64K test vectors per Burst. Program developers working on applications that have scan chain lengths greater than 64K should break up the device chain and generate the tests using multiple scan paths.

  9. What options are available for customizing Scan Pathfinder tests?

    Scan Pathfinder provides a number of options that can be used by Developers to customize the boundary scan tests generated by the software. These options are input to the test generator via the Scan Pathfinder User Options file (ScanPUserOptions file located in the test project General folder).

    The options file can be automatically created by setting options located in the Scan Pathfinder Setup and Analysis window or it can be manually created and modified using a text editor. The following is a brief description of the options that are available to the test developer.

    • Power Options – Specifies the name of the Power Up and Power Down subroutines to use during the boundary scan tests and whether or not to leave the UUT powered up during boundary scan fault diagnosis.
    • Logic Levels – Specifies the logic level voltages for the D/S nails that will be used during the boundary scan tests. Complex multiple logic level families can be specified by editing the user options template to include a USER_LVLA procedure that specifies the ASSIGN LGC test language statement.
    • TAP Options – Allows developers to override the default scan path configurations calculated by the software and directly define the scan path and Test Access Pins.
    • Non-Test-Options – Specifies a list of UUT nodes or devices that the developer does not want the Scan Pathfinder software to test.
    • Node Count Limits – Specifies the maximum and minimum number of nodes/nails to include in the boundary scan Opens, Interaction, and Interconnect tests. Users can set these limits prior to test generation to ensure that the boundary scan tests will not generate tests that require more real nails than are available in the target tester.
    • Use BSC Node Groupings – Forces the test generator to use the node groupings specified in the Boundary Scan Configuration file when it is generating the Interactions and Opens test. This option is useful on multiplexed test systems when regenerating the boundary scan tests after the fixture has already been built. It can be used to make sure the generated test will not cause multiplexing conflicts.
    • Test with TAP Port Only – Forces the test generator to generate a boundary scan interconnect test that only uses the boundary scan TAP nails (it will test pure boundary scan connections without using any tester nails beyond those connected to the TAP pins). This feature can be used to run boundary scan Interconnect testing of pure boundary scan nets before the ICT test fixture is available.
    • Isolation Mode – Controls the behavior of the Inhibit and Disable routines that are generated by the software to isolate the non-boundary scan parts on the board during the boundary scan tests.
    • 1149.6 Transition Times – Specifies the minimum wait time required for AC input cell pins to detect changing output pins during the Interconnect test.
    • RunBIST Clocks – Allows developers to define a custom SET CLOCK statement and timing parameters to be used while executing the RunBIST tests.
    • Path Initialization – Allows developers to define a custom initialization sequence that they want to execute to support interfacing with scan bridge link type devices.
    • Use HIGHZ/Bypass – Instructs the test generator to load the HIGHZ or BYPASS instruction into the non-target devices during the OPENS test rather than EXTEST – which shortens the scan chain and reduces overall test time.
    • BIDIR Bus Test – Option that can be turned on to have Scan Pathfinder generate an Interconnect test that verifies each pin on a bidirectional bus can both drive and sense.

    In addition to the above options, users can automatically include custom code in Scan Pathfinder tests by utilizing the traditional Automatic Test Options (ATO) file.

  10. What is the typical process for developing Scan Pathfinder tests?

    The Scan Pathfinder test generator software was designed to automatically find the boundary scan parts on your PCB design and recognize how the UUT scan paths are constructed. The software does this by analyzing the circuit interconnections, project library files, user option files and test selection inputs. The Scan Pathfinder software will generate an independent boundary scan test program file (BTP file) which, for convenience, can be translated and debugged separately from the Analog, Digital, and Hybrid test programs. At the completion of debug all the independent test programs can be combined into a single test program using Teradyne’s merge utility.

    The steps below show the typical steps involved in generating Scan Pathfinder boundary scan tests.
    1. Use Teradyne’s TS Development Pro (Win 7 TestStation Pro Ver 7.1) software to create a test project and import PCB CAD data.
    2. Obtain BSDL models for all boundary scan parts on your board and place them in the Project or Site Boundary Scan Library.
    3. Define boundary scan test generator options using Scan Pathfinder Setup window and boundary scan user options file.
    4. Generate and analyze boundary scan fault coverage and test generator report files.
    5. Modify options as needed to optimize tests and generate boundary scan test program.
    6. Translate and debug boundary scan test program on the target TestStation tester.

  11. How do I know how effective the Scan Pathfinder tests are at detecting faults?

    Scan Pathfinder produces three report files that developers can review to determine the effectiveness of the boundary scan tests on your board application.

    • The DigitalAtgResults file is a text report file located in the project report folder that contains message and status information related to the most recent run of the digital and boundary scan test generators. Developers should review this file after running test generation to make sure the digital and boundary scan tests were successfully generated.

      The types of information contained in this file includes: a summary of board statistics, syntax or structural problems with BSDL models, a list of nodes that will be used as boundary scan compliance nodes, a list of the nodes and pins tested by each boundary scan test, a list of the node ID’s assigned to each boundary scan node and any Warning or Error messages that were produced during the test generation process.

    • The BscanConfiguration file is a text report file located in the project report folder that contains summary information about the boundary scan board topology, scan path configuration, options and test types related to the most recent run of the Scan Pathfinder test generator. Developers should review this file after running test generation to make sure the generated boundary scan tests reflect their expectations for how the board should be tested.
      The types of information reported in this file include: number of boundary scan devices, number of scan paths and their configuration, number of pure boundary scan nodes, test generator options that were set by the user and list of nodes that are tested by each Scan Pathfinder test type.

    • The BscanFaultCoverage file is a text report file located in the project report folder that contains detailed information about the Shorts and Opens coverage of the most recently generated boundary scan tests and how each net on the board was categorized by Teradyne’s circuit analysis software. Developers can review this file to understand which defects can be detected and which defects cannot be detected.

    For Opens test coverage, the report creates a table for each boundary device showing each device pin and whether or not an open pin defect on that pin is detected by the Scan Pathfinder Hardware, Opens, or Interconnect tests. For Shorts coverage, the report calculates the number of potential shorts for the board and how many unique shorts are detected by each Scan Pathfinder test.

    The report also contains lists of unnailed conventional and external boundary scan nodes (where test coverage could be improved by adding a test nail) and nailed internal boundary scan nodes (where nails could be removed without reducing fault coverage).

    Note that the information reported in the above report files can also be reviewed using Scan Pathfinder’s analysis user interface, by selecting the View menu. An example of an Opens report using the Scan Pathfinder analysis window is shown here.

  12. What is the typical process for debugging Scan Pathfinder tests?

    Scan Pathfinder boundary scan tests are different from traditional digital device tests and require a different debug process. Scan Pathfinder generates many tests, each designed to detect specific faults - and these tests depend on the simultaneous operation of all the boundary scan parts on the UUT and the collaborative application of drive and sense values via boundary scan pins and Driver/Sensor nails.

    To deal with this complexity and ensure precise diagnostics, the TestStation Run Time System (RTS) relies on a separate Boundary Scan Diagnostic (BSD) task to interpret the test failures results and recommend repair actions. The BSD task references a test project DIAG_FILE that is produced by the Scan Pathfinder test generation software and a Boundary Scan Results (BSR) file that is automatically generated by the RTS whenever Scan Pathfinder tests fail. The BSR file contains the result values that were sensed by the TDO pins on all the scan chains as well as the values that were sensed by the tester D/S nails. The BSD task compares the result vector data in the BSR file with the expect vector data stored in the DIAG_FILE, analyzes the failures and produces the appropriate diagnostic message.

    Because of this design, debugging Scan Pathfinder tests is not like debugging traditional device based digital tests. Operators cannot simply change the boundary scan test vector data using the standard TestStation Burst Untranslator and Waveform Display debug software. Most test vector changes require the operator to modify the test generator options and re-generate the boundary scan tests.

    The steps below show the typical steps involved in debugging Scan Pathfinder boundary scan tests.
    1. Run boundary scan tests in Test mode and examine the bscan failure diagnostic report to identify failing tests, nets, and pins. Debug complexity can be reduced by concentrating on debugging tests one at a time (Hardware Test, Interconnect Test, Opens Test, Interaction Test).
    2. Use Scan Pathfinder’s Values or Brief diagnostic message format to obtain verbose information on failures and gain insight on on pin, cell, and net failures.
    3. Modify Scan Pathfinder test generator options and re-generate tests as needed to correct reported failures:
    a. Correct, modify, or remove device BSDL models
    b. Correct or modify PCB circuit description
    c. Modify Scan Pathfinder options (notest failing nets, re-define scan path, increase 1149.6 wait times, define path initialization)
    d. Update initialization, isolation, or compliance enable vectors

    A command line based BSDEB mode is available from the RTS that can be used by expert users to view the boundary scan vectors and their associated boundary scan pins and cells. Refer to the Test and Debug chapter of the Scan Pathfinder II User’s Guide for more information on the Scan Pathfinder debug process.

  13. What Teradyne ICT test systems support Scan Pathfinder II?

    Scan Pathfinder II is only supported on TestStation UltraPin I or UltraPin II based systems running the most recent TestStation Pro 7.1 or later software.Scan Pathfinder II does not support older GR228X tester types including 2280, 2281, 2281A, 2283, 2284, 2286, 2287, 2287A, 2287L, 2287LX, and all TS8X models.

  14. What do test developers need to develop Scan Pathfinder II boundary scan tests?

    Program developers will typically develop and debug boundary scan tests using an offline PC workstation that is configured with the Windows 7 operating system and the latest TestStation software suite (Version 7.1 or later). Generating boundary scan tests requires that the offline PC be licensed to run the Scan Pathfinder Program Prep software.

    After the boundary scan tests have been generated successfully on an offline development station, they can be moved to a TestStation test system where they can be executed using the TestStation Debug Pro or Production Pro user interface. In order to run the Scan Pathfinder run time and diagnostic software the tester must be licensed to run the Scan Pathfinder Test and Diagnostic license and possibly the Advanced Diagnostic license (if the test vectors include IEEE 1149.6 test features).
  15. What will Contract Manufacturers need to run Scan Pathfinder II tests?

    Most Contract Manufacturers are typically consigned an in-circuit test fixture and program by their OEM customer. They do not typically develop the in-circuit fixture or program. These Contract Manufacturers will be delivered a fixture and a test program that already has the in-circuit and boundary scan tests already integrated.

    For these Contract Manufacturers all they need to do is make sure that the Boundary Scan Diagnostic licenses are enabled on their production test systems. If the Contract Manufacturer is authorized to make changes to the boundary scan production tests (to support ECO or part changes), then they would need the Scan Pathfinder Development software available on the tester or an offline PC.
  16. ‚ÄčCan I upgrade existing Scan Pathfinder tests with new test capabilities?

    Existing boundary scan programs that were developed using Scan Pathfinder I will continue to work on TestStation systems loaded with the latest software. However these Scan Pathfinder programs, generated using older versions of Scan Pathfinder, cannot be upgraded to include testing of differential and AC coupled IEEE1149.6 nets.

    To take advantage of the advanced fault coverage and diagnostic capabilities of Scan Pathfinder II, manufacturers must re-generate their boundary scan test and diagnostic files using the latest TestStation Development software – and debug any new tests that are generated.
    The original boundary scan user option files can be re-used as an input to the Scan Pathfinder II software when re-generating the tests to control which nodes are tested and how the nodes are grouped for each test.