Teradyne - Semiconductor Test Division

Semiconductor Test is a lead-ing supplier of semiconductor test equipment for logic, RF, analog, power, mixed-signal, and memory technologies. We deliver test solutions to developers and manufacturers of a broad range of integrated circuits, packaged separately or integrated as System-On-a-Chip (SOC) or System-In-Package (SIP) devices. ICs tested by Teradyne are used in computing, communications, consumer, automotive, identification, and internet applications.

Tiger
Advanced Digital with Silicon Germanium Technology
  • Silicon Germanium digital technology for Real I/O, DUT-cycle-time programming with single burst test patterns
  • Gigabit data rates with full I/O to 1.25 Gbps, 1.6 Gbps differential, and 3.2 Gbps for ultra-high speed applications
  • TwinMode™ electronics for single-ended, differential, or common mode on every pin
  • Same cycle source synchronous compare and capture with wide data eyes
  • Digital Signal I/O separates vector and waveform data for simplified programming and debug
  • Softscale™ scalability for software upgrade of digital system speed

The Tiger system delivers up to 1024 I/O channels, with Twin Mode™ pin electronics that support true differential, common mode, and single-ended I/O test on every pin. There’s no loss of channel count for high performance digital devices. And Softscale™ scalabilitylets you upgrade digital speed through software for selected pin groups to match your test applications. You easily configure the system with the pin count and capability you need for single insertion device testing – reducing test time, increasing throughput, and lowering test cost per device.

Tiger digital supports drive, strobe, and I/O switching at up to 800 Mbps within a single pattern. The unique Real I/O™ pattern generator uses silicon germanium technology to deliver complete functional and timing margin checks in one pattern burst, at any digital date rate. And DUT-cycle-based timing lets you generate test programs in device time, not limited by the system’s vector instruction rate.

Tiger Digital Signal I/O maintains vector and analog waveform data separately. Instead of a traditional approach that treats digital and analog as the same type of data, the Tiger system sets vector data as absolute and digital signal data as sampled waveforms - either known source data or captured data to be analyzed.  This approach significantly simplifies pattern generation, slashing program development and debug time, and getting devices to market faster.

For high-performance, high-speed applications like SerDes, PCI Express, HyperTransport, and RapidIO, the Tiger system delivers comprehensive functional test at speed. The SerDes Port Qualifier (SPQ) offers complete testing of SerDes ports, with at-speed functional and jitter test in production.  The Tiger Source Synchronous Pin Electronics (SSPE) along with the Real I/O pattern generation provide single-ended or differenctial signals covering all device waveform and time domain combinations. The Tiger system with SSPE achieves wider data eyes, improving test quality and enabling higher yields and lower cost.

Analog >