As semiconductor geometries become smaller and greater complexity is pushed into ICs and packages, it is increasingly difficult to maintain high fault coverage. The traditional combination of automated test program generation (ATPG) and scan has enabled very high fault coverage but an increasing portion of complex circuits are moving out of reach of these techniques. Further, testing in “test modes” can mask faults that are only expressed when the part is operating in its functional mode. System Level Test (SLT) is a test technique that addresses these challenges, a functional test where the DUT runs as it would in its end application, including interfacing with real hardware peripherals and running real software. By running the DUT as it would in its end application we can test the interfaces between IP blocks without writing challenging test vectors; test the interactions between IP blocks; test HW/SW interactions; and run for a longer time to help reveal intermittent faults. This presentation will discuss what SLT is, and how it can improve final product quality and reduce time to market.