Testing power semiconductor devices at high voltages and/or high currents carries the risk of damaging devices or test equipment through arcing or overheating. Smaller chip sizes pose even bigger challenges for tests at the wafer level. Wafer test of power semiconductor poses some quite specific challenges with test currents of more than 100 Amps and test voltages exceeding 1 Kilovolt. Well-proven for “classical” devices fabricated in silicon technology, examples being rectifier diodes, IGBTs, and power MOSFETS, high voltage arc suppression technology provides spark-free probing for devices made in Si, SiC, and GaN technologies with their inherent capability for smaller chip sizes and risk of sparking during wafer test. This presentation will discuss a process for reducing arcing during wafer test, thereby reducing the cost of replacing the probe and the damage to the wafer. We will review why and how to detect and control this arcing during wafer probe testing, and the causes and how they may be resolved to ideally lower the cost of probe testing by increasing the time between probe changes due to arcing.