The phenomenon of semiconductor scaling, Moore’s Law, has increased the device density per unit area while delivering higher performance, low power consumption and low-cost devices, creating an even more complex system. Production testing of these systems to ensure overall system performance, quality and reliability becomes a difficult problem. System level test (SLT) fills the gap where traditional structural and functional testing falls short and has become an important test insertion in the semiconductor test flow. This presentation will discuss the trend of this fault coverage with a semiconductor test system, which functions as multiple logic testers where each logic tester operates independently and asynchronously from the other despite the complexities and additional test cost. We will also discuss a test system which can conduct asynchronous parallel testing on multiple devices and explore how asynchronous parallel test makes SLT a lower-cost insertion and high-volume manufacturing (HVM) production-worthy. In addition, massively parallel asynchronous test data and upstream data analytics can enable adaptive test decisions to be made between wafer, functional and system level test further reducing the overall cost of test.