Transistor counts and the number of IP cores for HPC devices continue to climb with new process nodes. Traditional GPIO-based scan strategies are becoming a limitation because they do not have enough data bandwidth. EDA suppliers are providing new solutions such as packetized scan data and scan over SERDES interfaces. There are also new EDA tools to perform functional test on ATE over the SERDES interface. This presentation will review these new EDA trends and how they impact test program generation and device bring-up. We will also discuss which of these new tools are likely to find wide adoption and why.