High current testing of 2-5mOhm FET RDSons require special attention to the magnetic field. Non-optimized layouts can lead to several hundreds of uV of magnetic interaction between the force and sense traces that can take milliseconds of time to settle. Since this settling happens while high current is being applied it can dramatically increase the heating on device contactor pins, reducing their lifetime. In this presentation, we’ll review our experience with reconfiguring a board with magnetic optimizations. We’ll compare the original layout of the magnetic field, where ther is almost no drop-off throughout the PCB area above and below the high current trace and the related sense lines are closely coupled to the force lines; and the optimized layout, where the FH and FL traces are stacked on top of each other and the sense lines follow a new, shorter path, resulting in the magnetic field and interaction being drastically reduced.