Scan has always been a key test item for SoC devices. With the ever-increasing number of gates, the test time for scan continues to increase. Customers face tough decisions weighing test time versus coverage. Increasing the scan bandwidth can be used to counter the ever-growing scan requirements but before considering how to increase this, customers must also consider other complexities. Complex hierarchies create challenges to implement the DFT required for scan. Additionally, the constraints on the number of pins available compounds the complexities, all of which points to a need to find new approaches to reduce the complexity and counter test time. One approach stems from IEEE 1149.10 specifications, in which Siemens has developed a solution using their Streaming Scan Network to achieve scan over SerDes. This presentation will explore the implementation Siemens has created for IEEE 1149.10, the test challenges and how UltraPin2200’s unique architecture solves them.