Advanced Digital Devices are experiencing exponentially increasing test challenges from multiple directions. The industry is responding by introducing new approaches to test that expect to disrupt the status quo. One key area of opportunity is in scan and structural test, with a number of emerging options that will improve efficiency and effectiveness. With more transistors to test and new failure modes due to advanced technologies, the amount of total test data volume continues to grow at an exponential pace. The existing standard approaches to DFT structural testing, such as scan, have encountered practical limits, in part due to data bandwidth from limited GPIO rates and limited or fewer pins available for scan. One of the new leading options to overcome these limitations is to utilize existing High-Speed I/O interfaces, which promises to provide much higher test data bandwidth while also reducing the number of digital test pins required. In addition, it offers exciting new opportunities such as leveraging the ability to perform DFT test across the silicon lifecycle, from ATE through System Level Test (SLT), and even through to the final in-field environment. This presentation will explore the benefits and test considerations of using HSIO interfaces in their fully-functional protocol configuration for structural test. It will describe Teradyne’s strong development partnership with Synopsys for their DesignWare HSAT and Test MAX ALE products, and how we are enabling the most advanced test solutions for the future of protocol-based test.