MIPI CPHY/DPHY is fundamentally different from typical single-ended or differential IOs, it is posing challenges to both ATE and SLT testing. A common test strategy adopted by most chip makers is Loopback, however, the loopback scenarios can be very complex.

In this paper, the author will introduce the challenges of MIPI CPHY & DPHY Test with an example of complexed Loopback scenarios. Performance characterization was performed on two major switch choices: high performance mechanical relays vs. high bandwidth CMOS MUX ICs. The study also covers other aspects such as cost and real estate.
The second goal of the paper is to discuss the lessons learnt during optimizing the high-speed loopback path on the DIB, specifically how to optimize the vias, which is the major bottleneck of the channel performance during a high-speed PCB design.