As the semiconductor industry continues to advance with smaller geometries and increased packaging complexity, testing these devices poses significant challenges. System level test (SLT) has emerged as a promising approach to address these challenges by enabling testing at a higher level of integration. This paper explores the use of high-protocol serial scan testing and discusses methods to overcome the associated challenges.

By leveraging standard protocols such as USB and PCIe, high-protocol serial scan testing offers cost-effectiveness and improved diagnostic capabilities. The paper highlights the benefits of SLT, the limitations of traditional scan methods, and the advantages of adopting high-protocol serial scan testing. It delves into the background of scan challenges, including limited pin count, increasing data volume, and advanced packaging constraints. The need for innovative solutions to ensure comprehensive scan testing in the era of chiplets and site count limitations in automated test equipment (ATE) is also addressed.

The paper categorizes scan testing into parallel scan and serial scan, emphasizing the growing trend towards serial scan adoption. Low-protocol serial scan reduces the number of required test pins, while high-protocol serial scan leverages commonly used mission mode protocols like USB and PCIe, enabling efficient and cost-effective testing.

Furthermore, the paper demonstrates the integration of high-protocol scan testing into SLT, showcasing its ability to test high-yield patterns at a lower cost of quality compared to traditional methods. The scalability and flexibility of SLT systems allow for parallel execution of high-protocol scan tests, enhancing overall test efficiency. Additionally, the seamless transition between ATE and SLT facilitates easy debugging and yield improvements. The scope of high-protocol serial scan testing extends throughout the lifecycle of a chip, encompassing wafer sort, final test, SLT, and in-field testing.