As the advanced digital ASICs increase their complexity and transistor count, there is an ever increasing need to move vast amount of digital information into and out of the DUTs. Outside DRAM, chip-to-chip communication happens predominantly over high-speed serial interfaces. Their data rates are ranging from 8Gbps NRZ to 112Gbps PAM4 per lane. The broadband frequency components in the serial signals span continuously from low RF range well into the microwave range. The corresponding serial signals travel over the long and complex channel topology from the instrument PE to DUT, compared to conventional on-DIB simple loopback path. Good signal integrity is crucial for ATE solution success.

This work summarizes the design process and signal integrity considerations for general high-speed serial instruments and their DIBs, focusing on the channel design and system-level validation. We are using the first UltraFLEXPlus serial instrument DIB, namely scope jack DIB, as the sample. It is a general-purpose text fixture that can work with multiple high-speed serial instruments. The DIB design has achieved one-spin success during the US20G Image Sensor PHY validation and prototyping. The overall end-to-end channel, including the instrument board and the scope jack DIB, achieved less than 1e-15 BER under a calibrated stressed eye at 20Gbps. The same design techniques and validation methodology are also applicable to other high-speed serial boards in general.