This paper delves into the optimization of the system-level test (SLT) strategy by focusing on two critical aspects: the interfaces between the system-level test board (SLTB) and the SLT tester, and the design and strategy for executing and sequencing tests. With the growing challenges posed by shrinking geometries and complex packaging in semiconductor testing, SLT has emerged as a crucial solution.

Efficient testing and future scalability heavily rely on the design of the SLTB interface. By capitalizing on the capabilities of the SLT tester, such as dual power supplies and high-speed serial interfaces like SPI, an abstract interface can be devised. This interface remains constant while the test requirements for Devices Under Test (DUTs) evolve. By employing a high-speed serial interface for testing, the SLTB can accommodate expanded input/output capabilities and integrate mock hardware using FPGA or supervisory test board processors. This design approach ensures consistent test interfaces, effectively optimizing the SLT test strategy regardless of device or DUT evolution.

The paper also explores test execution and sequencing, specifically focusing on two patterns: software based self-test (SBST) and tester-driven testing. Each approach presents trade-offs in terms of development time, test execution time, debuggability, and ease of making changes. Leveraging tools like Teradyne Test Executive empowers test engineers to easily write, sequence, and modify tests, enhancing flexibility and reducing development time. Conversely, SBST relies on specialized embedded resources, making test changes more challenging.

By thoughtfully considering the design of the SLTB interface and test execution, semiconductor manufacturers can optimize their SLT test strategy. This optimization leads to high-density manufacturing, efficient utilization of board space and features, and streamlined testing processes. These improvements enhance testing efficiency and flexibility, facilitating smoother transitions from bench-scale to high-volume manufacturing, and ultimately ensuring the production of high-quality integrated circuits.