Siemens has introduced Tessent™ Streaming Scan Network (SSN) IP that can be included in devices to help with reducing scan test data volume and to allow efficient testing of multiple cores in parallel. SSN support two basic modes – “tester-compare” and “on-chip compare”. On-Chip Compare allows for reduced scan test time with the parallel testing of any number of identical cores. This paper will begin with an overview of On-Chip Compare, explaining its functionality, and how it interacts with SSN’s other operating mode, Tester-Compare, and the impact this has on the SSN bus when failures are mapped to cores. Next, challenges that come with using On-Chip Compare will be covered, starting with the ATE conversion process. Information embedded in the STIL or WGL that describes how the device has implemented SSN must be extracted to ensure the test is performed properly. When the test is being performed, this information is used identify failing device cores, and alter the test setup with JTAG to ensure that, when necessary, all required diagnostic information is collected in a manner compatible with Siemens’ diagnostic tools.