The semiconductor wafer test market has been limited by signal delivery and/or parallelism of physical device layout constraints with the active area of the probe array. UltraFLEXplus breaks through these barriers with a new PTL architecture called Universal PTL. Keeping the existing architecture delivering proven system rigidity and opening the center region for applications space from existing architectures offers a new market opportunity for high parallelism testing starting with the automotive sector and potentially reaching more segments.

The new DIB frame and center stiffener provides a wider center region to over 300mm and makes it possible to strategically contact and simultaneously test devices across a 300mm wafer. This approach will reduce the total number of contacts or touchdowns to completely test the entire wafer. The proven interface of UltraFLEXplus already provides the significant system rigidity needed for massively parallel probe arrays. Opening the center region allows for a strategic placement of these testable probe sites that distributes the load over the 300mm wafer. In conjunction with routing signals to each of the DUTs, the UltraFLEXplus system architecture optimally manages these higher forces.

Teradyne’s competition already has products in this market space and has reached saturation according to Customers and Probecard Suppliers. The Competitor is limited to lower site counts due to probe force limitation with their architecture and maximum signal delivery. Teradyne is targeting a market entry solution that will deliver a 63% increase in the parallel site count, a 43% decrease in touchdowns with the Q12 tester while maintaining existing force loads as delivered today on the UltraFLEXplus platform architecture.