This presentation outlines the strategies employed in the development and testing of AP class chips using the Teradyne UltraFLEXplus (UFP) platform. Our project leverages advanced technologies to integrate Chip Probing (CP) and Final Test (FT) processes, achieving improved efficiency and quality. We begin by examining the technical advancements that enable high site count testing on the UFP platform. This section introduces how to use the new PACE architecture of the UltraFLEXplus platform to address the challenges in Load Board design for high site count. It also ensures the parallel test efficiency (PTE) of each site. Additionally, we discuss increasing CP flow test coverage, including strategies for ensuring site consistency in CP binning and shifting more tests from FT to CP such as Memory-BIST etc. The implementation of the MIPI switch in the current project is also highlighted.

The second section focuses on improvements in quality and efficiency through the development of a robust library of IPs common codes, characterization, and Efuse CBB. We also discuss the integration of IG link, Git, and DevOps practices, alongside custom tools like STDF analysis tool, Shmoo result analysis tool, and testing program information extraction tool. Finally, we analyze the cost implications, covering common Test-Time-Reduction (TTR) strategies for System on Chip (SoC) products, the financial benefits of high site count testing, and the cost-effectiveness of increasing CP flow test coverage.