Overshoot on the VCE signal during a short circuit test on an IGBT, SiC or Mosfet always manifests at the time the device is switching its state from On to Off. This overshoot represents a threat to the integrity of the device because in some cases the peak value of this signal can surpasses the breakdown voltage or even the maximum electrical specifications the device can handle, therefore damaging the device. In the case of Power Discrete applications when designing a PCB that will execute a whole flow of tests (including the Short Circuit Test), parasitic inductances are introduced to the circuit creating or increasing the overshoot the device will experience. There are several techniques that are applied in the field to reduce this effect, like changing the Rg resistor on gate, manipulating the VGE value, or adding a snubber circuit on the design, but these techniques often do not resolve the issue completely and in some cases generate other problems for the field engineers. This project proposes a dv/dt feedback control method that uses a capacitor placed in parallel to the miller capacitance of the device, introducing a current di/dt to the control circuit in order to change the dv/dt response of the device, therefore reducing or even eliminating the overshoot generate by the application itself.