Wafer Level Burn In for SiC Power Devices | Teradyne

Between 2022 and 2028, the largest revenue drivers for the Power Semiconductor market will be in EV, Automotive, Industrial Motors and Consumer Electronics. EV (20% CAGR 2022-28) is expected to continue significant growth into the next decade due to environmental and sustainability government initiatives. Morningstar forecasts that EVs will account for about 40% of all vehicles sold worldwide in 2030.

One of the key innovations in power semiconductors is the use of wide bandgap (WBG) materials like silicon carbide (SiC). WBG materials have a higher efficiency, can hold off higher voltages, and operate at higher temperatures than the typical silicon (Si) devices. Therefore, an EV using SiC chips in the traction inverter can have 10% longer range (or a 10% smaller battery, therefore lower price) than an EV with Si chips. However, these SiC devices have unique challenges which ultimately lead to a much lower yield, which on a typical SiC device wafer can be as low as 70%, as compared to a typical silicon power device wafer which has a yield of over 95%. It is important to weed out known-bad devices prior to singulation so as to avoid the expensive step of packaging such failed devices.

Some lessons learned from 50+ years of Si device production are applied to SiC. One such lesson is the use of wafer-level burn-in to do highly accelerated life tests (HALTs). These tests stress the power device at elevated temperatures with basic DC testing to ensure all failed devices are weeded out.

This paper describes the technical reasons for doing WLBI for SiC power devices. We will discuss the significant drawbacks of SiC crystal growth as compared to Si, as well as unique device physics of the SiC MOSFET. We will discuss how WLBI is done, and why we believe that it will be necessary process qualification step for the foreseeable future. Finally, based on the potential growth of SiC market, a model of the total available market (TAM) will be presented.