System Level Test – A Primer: White Paper

As semiconductor geometries become smaller and greater complexity is pushed into chips or packages, System Level Test (SLT) is becoming essential.

Peter Reichert, System Architect for Teradyne’s System Level Test division discusses what System Level Test is, and how it can improve final product quality and reduce time to market.

System Level Test (SLT) is testing a device under test (DUT) as it is used in the end-use system, by merely using it rather than creating test vectors, as is done with traditional automated test equipment (ATE). Tests are still written but in a different way…