Integration circuit (IC) fabrication is very complicated, as many manufacturing steps have to be executed on the same wafer. All fabrication steps are subject to errors, wafer defect patterns are the results of various problems in the fabrication and wafer test process. Thus, the wafer map defect patterns can be used to identify sources of errors in the manufacturing process.

Recently, local defect pattern recognition has attracted a lot of research interests. The results of wafer test are usually presented in a wafer map, which gives locations of failed dies in a wafer.

There is plenty information of Machine learning and wafer map recognition patterns on published research, the idea of this paper and project is to use this information as leverage to create a pattern recognition system for Teradyne testers, that will detect patterns automatically when running production on the clients’ sites. This will give added value to our services and will help our clients to recognize manufacturing issues quickly.