The 3nm process for newer semiconductors offers numerous advantages, including denser transistor, performance improvements and enhanced power efficiency. However, packing more transistors in the same area increases complexity and carriages new challenges for testing. The number of cores grows while the pin counts available remain constant. Traditional scan method may result in inefficient test time and vector memory utilization. The Tessent Streaming Scan Network (SSN) introduced by Siemens aims to overcome these testing challenges by reducing the scan test data and enabling parallelism of multiple cores. The UltraFlexplus tester supports SSN in two modes: On Chip Compare and Tester Compare. Additionally, the improved capabilities and performance of the UltraFLEXplus digital instrument UltraPin2200 provide larger and pooled vector memory shared across channels, larger scan capabilities, and more flexible digital channels allocation. The objective of this paper is to explore the advantages of implementing the SSN mode On Chip Compare versus the traditional scan testing. These benefits might include test time reduction, vector memory utilization optimization, and more rapid test program development.