Getting an integrated circuit (IC) from design to test is an arduous process that encompasses a number of steps. It is an iterative process that can take months and with shortening time to market windows, engineering teams are being asked to support several chip designs – sometimes five or six new designs – in the same timeframe that they used to manage a single device. Of course, the first question they ask themselves is how am I going to get more work done, in less time, with the same or fewer resources?
One area of significant inefficiency is the time it takes to move test programs from development to production, and specifically the debug process. Design and bench engineers use one set of tools to create test sequences, while test engineers working with the ATE, are typically talking at a much lower level, in levels and timing, and their vector is ones and zeros so there is a language gap between the tools used by the test engineer and those used by the design engineer that complicates debugging. Small improvements in any part of this process can greatly reduce overall cycle time.