Teradyne Users Group
TUGx Global Seminars are a series of one day, free events held throughout the world both in-person and virtually. These local seminars provide an avenue for Teradyne to share best practices and new test methodologies, ensuring content is relevant to the local audience and empowering our customers to get the most out of their Teradyne technology.
Abstracts
Advanced Digital/SOC
Siemens Streaming Scan Network Overview
Siemens has introduced a new technology Tessent™ Streaming Scan Network (SSN) for delivering scan data to IP blocks. Streaming Scan Network also known as SSN is an EDA IP that includes methodology for generating ATPG and diagnosis. Once integrated in devices, SSN will reduce scan test data volume and allow efficient testing of multiple cores in parallel. It enables the designer to lower risk and development, in regards to ATPG scan testing. SSN is a bus distribution network along with local IP block that generates DFT signals that streamlines data distribution in the design. SSN support two basic modes – “tester-compare” and “on-chip compare”. Within each of these modes there are options to support “throttling” and “rotation” of scan data to fully maximize the bandwidth of the scan data bus and minimize pattern execution time. Each of these use cases have potential new requirements in the ATE. This presentation gives the user a starting point to understanding SSN and key differences in use cases.
Siemens Streaming Scan Network Tester Compare Operation Overview
Siemens has introduced Tessent™ Streaming Scan Network (SSN) IP that can be included in devices to help with reducing scan test data volume and to allow efficient testing of multiple cores in parallel. SSN support two basic modes – “tester-compare” and “on-chip compare”. This paper will review the basics of the SSN Tester Compare operation and then review recent updates made to IG-XL on the UltraFlexPlus to assist the user with implementing efficient test instances for devices utilizing SSN Tester Compare. Topics covered will include how to encapsulate data mapping information extracted from the EDA simulation output into binary pattern files, review new data objects to efficiently identify failing cores after an SSN pattern burst, and review new language to allow the user to easily apply core masking without modification of the SSN pattern files.
Siemens Streaming Scan Network On-Chip Compare Overview
Siemens has introduced Tessent™ Streaming Scan Network (SSN) IP that can be included in devices to help with reducing scan test data volume and to allow efficient testing of multiple cores in parallel. SSN support two basic modes – “tester-compare” and “on-chip compare”. On-Chip Compare allows for reduced scan test time with the parallel testing of any number of identical cores. This paper will begin with an overview of On-Chip Compare, explaining its functionality, and how it interacts with SSN's other operating mode, Tester-Compare, and the impact this has on the SSN bus when failures are mapped to cores. Next, challenges that come with using On-Chip Compare will be covered, starting with the ATE conversion process. Information embedded in the STIL or WGL that describes how the device has implemented SSN must be extracted to ensure the test is performed properly. When the test is being performed, this information is used identify failing device cores, and alter the test setup with JTAG to ensure that, when necessary, all required diagnostic information is collected in a manner compatible with Siemens’ diagnostic tools.
Productivity Tools: Complementing Core Software to Deliver Enhanced Development Efficiency
The Productivity Tools suite in eKnowledge has grown from a small collection of apps-developed useful utilities to an essential toolkit in achieving faster debug and time-to-market. While Teradyne’s core software delivers tester-focused improvements in every release, Productivity Tools complement our core software by focusing on enhancing the user experience and efficiency. By combining customer needs and requests with a rapid development and release process, tools that are created by local teams to address gaps or customer requirements can now be picked up and further developed, productized, and supported to allow delivery to the wider customer base.
As a result, apps engineers now gain access to an ever-expanding toolset to make their jobs easier and achieve impressive results. This presentation will cover the latest collection of Productivity Tools on the ETS-800 and IG-XL based platforms, the results apps engineers have seen, and how to quickly get up and running using the tools.
Tuning UVS64 Bandwidth Setting To Improve Performance
Now more and more projects pay attention to their digital ability and performance. To improve the yield rate on the extreme condition, the SHMOO and VMIN performance are considered, especially the Power which has big current. With the low Voltage and big Current, the Power will has large Droop and Kick during dynamic load, which may cause Pattern test fail. UVS64 has good Droop and Kick performance to match the requirements, but it can’t reach its best performance if BW is not set correctly. The BW value must be set according to the DIB bypass capacitance and ESR value, then the Power can be close to its best dynamic performance. The paper will introduce how to manage a good PI performance on DIB design, and calculate the BW value based on the DIB bypass capacitance and ESR value on programming, and after that how to tune the BW value by analyze current and voltage profile to get the best performance. With all the effort, SHMOO and VMIN can be improved.
Generating ASCII Scan Fail Logs on UltraFLEXplus – ScanFalcon
The UltraFLEXplus scan fail data logging performance has been optimized for producing data in STDF format using the STDF V4-2007.1 scan extension in a high throughput production environment. The major EDA vendors can directly extract the required information for their diagnostic tools from STDF. However, when doing Engineering debug there may be times where the preferred workflow and output format is an ASCII-based fail log file directly written from IG-XL. ScanFalcon is an IG-XL Custom Data Consumer which can utilize the same data packets used to create the STDF output file and transform that packet content into an ASCII fail log. It supports creating output in formats compatible with major EDA vendor tools or allows the user to customize the ASCII content via custom format definition files. While there is a slight throughput impact, ScanFalcon can take full advantage of the optimized hardware fail data transfer and the bulk of the processing is done outside the main IG-XL process. This paper will describe ScanFalcon, how to use it in IG-XL programs, provide an overview of its customization capabilities.
PortBridge Expedites Complicated SOC Debug by Integrating Comprehensive Industry Tools
Testing SOC CPUs, like ARM based processors, on Automatic Test Equipment (ATE) presents unique challenges to engineers as device functionality cannot be confirmed through DFT alone. Production tests require an additional measure to evaluate functionality, typically accomplished by having a firmware engineer develop an ATE specific image. Since developing this firmware is predictably debug intensive, resolving issues on the ATE without tooling support can be a cumbersome undertaking. PortBridge provides the capability to run a high-level debug tools like ARM Development Studio or OpenOCD directly on the DUT using the ATE, reducing debug time and simplifying the bring-up process. Integration with these programs allows firmware engineers the ability to develop directly on the ATE on an industry-standard toolset and eliminates the need for time consuming simulation or emulation. Additionally, to allow collaboration across geographically distributed teams, PortBridge provides the ability to remotely connect to and debug the DUT.
How PortBridge’s Amplified Test File Feature Maximizes Analog Functionality Debugging
Embedding analog functionality into standard protocol testing has always been a challenge. Our PortBridge solution provides easy to use, out-of-the-box support for standard protocols, including test program APIs, remote access, and automatic design file integration. It also provides a mechanism for parsing files that the Design and DFT engineers already generate as part of their workflow. These files can be loaded, executed, and debugged on the ATE with no conversion needed. Incorporating analog instrument control in line with standard protocol operations allows files to be used directly from the design environment with sequences of protocol transactions and analog operations. The PortBridge toolset gives the user the ability to debug specific problems easily. At production time, everything can be optimized for maximum performance. This opens the door for a new method of testing that maintains design time concepts of abstraction and removes time-consuming translations into ATE specific formats.
PortBridge Integrates On-Die Sensor Technology into the Test Environment Seamlessly
On-Die sensors are revolutionizing system health and performance monitoring in the field as well as during ATE test. Device complexity is increasing, test program complexity is increasing and time from silicon arrival to product ramp is decreasing. Test engineers need solutions they can integrate quickly into their existing test flows that allow them to reduce debug time while improving test coverage. proteanTecs provides cloud based, technology agnostic data processing on their wide range of supported die sensors. This includes real-time decision models and uploading captured results to the cloud for cross-insertion learning. PortBridge integrates proteanTecs solutions seamlessly into IG-XL, providing a clean optimized, multi-site interface. This talk will cover customer successes in this area and new features added to further enable customer data collection and analysis.
The DSP Difference Between UltraFLEX+ IPQ8 and IP750
UltraFLEX+ IPQ8 is Teradyne’s new generation UltraFlexPlus-based image sensor ATE test platform. Derived from UltraFLEX+ Q12, UltraFLEX+ IPQ8 has a lens tube space for 150mmx150mm internal halogen illuminator unit for image sensor test and towerless prober docking for optimal signal paths. In terms of instruments, UltraSrial20G-DP, a new image capture instrument is designed for IPQ8, it can capture image sensor outputs based on the DisplayPort protocol up to 9.9Gbps.
Same as IP750, the existing Teradyne image sensor test platform, UltraFLEX+ IPQ8 also has IDP (Image data processing) subsystem which is the image data processing infrastructure that is built on top of the UltraFLEX+ DSP subsystem.
UltraFLEX+ IPQ8 IDP subsystem enables superior performance by improved backgrounding capability and more optimized integration of software and hardware, it is being developed to offer better technical capabilities then IP750.
This document introduces the difference of DSP concept between UltraFLEX+ IPQ8 and IP750, how to convert the IDP program from IP750 to UltraFLEX+ IPQ8 and the test time result comparison of them.
Using Limit Set to Achieve Diverse Binning Requirements
In order to meet various test requirements, the number of test items for larger SoC device is increasing day by day. To analyze the results of test items, it is needed different binning methods to find the test results of the test items in efficiency for specific test items. There are many methodologies to accomplish binning in tested result, and using limit set is a one of faster and flexible method in IG-XL. Limit set can carry out multiple binning requirements application, such as normal usage of binning which stops the testing immediately when the test item is failure. The other binning methods, the binning result of the test will be judged after a numbers of test items to expected bin. In another word, the test result is sorted by specific group instances or block with the failed items. In addition, it is also able to manage suppress binning application for developing, debugging and production requirements. Limit set is an existing feature in IG-XL to support and maintain the diverse binning function for test engineers and production engineers prosperously.
Concurrent Test Capabilities on the UltraFLEXplus
Using concurrent testing as a method to reduce test costs has been on the radar for more than a decade now. Concurrent testing can have advantages in many different applications. Some may think about doing analog or parametric tests while the internal MBIST is occupied with a longer Flash tests, testing different modules with different LBIST tests at the same time or simply testing 2 ports simultaneously. Any of these methods can reduce touchdown times or test program runs significantly.
However, in many cases so far, limitations of the device’s or the tester’s capabilities have prevented the introduction of concurrent testing. Now, the architecture and instrument features of the UltraFLEXplus like the asynchronous pattern starts and the increased ratio of patgens per instrument can make concurrent testing easier.
This presentation describes the work done to demonstrate concurrent test capabilities on the UltraFLEXplus. It will show different use cases and how they are being implemented on the UltraFLEXplus. It will also describe differences from the existing UltraFLEX instruments and the advantages of the new PACE architecture for concurrent testing.
ADAS Device with Best ATE Solution – Based on UltraFLEXplus
As the development of autonomous vehicles, ADAS will be probably next economic growth point, especially for semiconductor market. Compared with consumer semiconductors, ADAS products have larger size and higher power consumption, thousands of pins and hundreds of current requirements; most of these feature's lead to ATE test challenges, such as load board application area, power droop/kick, high speed signal loopback. Except for above, high site count is growing forward to decrease cost.
UltraFLEXplus is the most powerful SOC test platform of Teradyne, bring a lot of priority for LSIC test. We will introduce the tester advantage of ADAS product, such as more DIB application area, flexible FRC, protocol aware, frequency counter etc. Also, we will share some general technical test experience for this device type. such as MIPI, PCIE, DDR, UFS, USB and so on. At the same time, some project design experience such as handler, DIB design experience will be mentioned.
Best Practices for Converting a J750 Test Program to the UltraFLEXplus
How easy is it to move from the original IG-XL platform, the J750, to the newest IG-XL platform, the UltraFLEXplus, and why would anyone want to do that? To make a conversion to UltraFLEXplus worthwhile, one must achieve lower cost of test through higher site counts and faster throughput by taking advantage of features of the UltraFLEXplus PACE Architecture. Furthermore, conversion needs to be as automated as possible using available tools.
This paper will discuss a successful J750Ex to UltraFLEXplus conversion for a power management device. We provide an overview of the conversion goals, the differences between the platforms that needed to be addressed, the available tools that facilitated conversion, and the challenges faced during the conversion process. On the hardware side, we discuss how instrument alignment to requirements affected DIB design considerations. On the test program side, we discuss workbook, pattern, and VBT conversion strategies. Lastly, we discuss how the project was able to meet its COT and correlation goals, providing a guideline for future, similar conversions.
IP750 New Image Capture Instrument for MIPI CSI-2 C-PHY/D-PHY Combo
In recent years, smartphones and other mobile devices has equipped with higher resolution CMOS image sensors that requires higher data rates.
MIPI CSI2 D-PHY and C-PHY specifies physical layer defined by the MIPI Alliance for image data exchange between image sensor and AP and widely adopted by many mobile devices. The MIPI D-PHY is a general differential transmission line consisting of two pins per lane. The MIPI C-PHY is a complex differential transmission line with three pins per lane. Since there is no clock line, it has the advantage of saving pin counts.
In addition to the MIPI D-PHY, which has been the mainstream interface for image transfer, more and more image sensor devices support C-PHY as well. We had released the image capture option, ICUL, ICUL1G and ICMD for high data rate. ICUL supports for capturing SMIA CCP2 data. ICUL1G supports for capturing the SMIA CCP2, MIPI CSI-2 D-PHY and custom serial output data up to 1Gbps. ICMD supports for capturing the MIPI CSI-2 D-PHY and custom serial output data up to 1.5Gbps.
Now, we introduce the new IP750 series instrument, ICMCD, which can measure image sensors that support C-PHY/D-PHY combo.
UltraFLEXplus Enhanced Features for Analyzing and Datalogging Pattern Bursts at the Pattern Set Element Level
As digital devices continue to increase in complexity, the number of patterns to be executed in a test program increases accordingly. Pattern sets provide a structure for users to execute a large number of patterns consecutively. These pattern sets may be atomic, consisting of individual patterns, or hierarchical, consisting of one or more atomic pattern sets. Executing large groups of patterns as a hierarchical pattern set offers benefits to overall test time. However, this introduces challenges in datalogging information and processing results for individual pattern set elements, specifically the atomic pattern sets which make up a hierarchical pattern set. Previous workarounds to circumvent these challenges have introduced overhead to the test program and in response, IG-XL has introduced new features to provide these capabilities with low overhead.
A new statement, TheHdw.Patterns.ExecuteSet, has been added to execute hierarchical pattern sets and return an array of IPatternSetResult objects. TheExec.Flow.FunctionalTestLimit (FTL) has also been enhanced to support logging Scan Test Record (STR). With the new statement and FTL, the user can datalog STR/FTR for each hierarchical pattern set element and within an element, the user can log FTR at the per-element or per-module level. The new language also allows the user to assign unique fail bins to individual elements and set the failing cycle capture limit per element. To further support these features, IG-XL has added new capabilities to the debug display tools including the Pattern Tool, Waveform Display, and Characterization Studio, which provide additional access for the user to debug individual elements of hierarchical pattern sets. By taking advantage of these new IG-XL features, users will receive the benefit of shorter test time while maintaining binning and datalogging granularity along with the ease of debugging individual tests.
Teradyne UltraEdge2000: A Platform for Edge Adaptive Test
Semiconductor manufacturers continuously seek to improve yield and reduce test time with adaptive test techniques. Most adaptive test today involves a long feedback loop with test results moved outside of the test cell and actions fed back at a later time, possibly several lots later. These situations will continue to exist in cases where either human supervision is necessary or analysis is done with data from several test cells. However, with advancements in machine learning and analytics, many companies are starting to develop adaptive test algorithms and techniques that could be used with data on a single test cell from within a lot and possibly even during a touchdown. There are legitimate concerns to deploy these on host controllers due to possibility of using compute resources and impacting IG-XL throughput. Hence the need for an edge compute device.
The UltraEDGE was designed to provide a flexible and secure environment to run analytics within a tests cell. This paper will demonstrate how a user can integrate the UltraEDGE for adaptive test within the test flow as well as across the touchdowns.
Using PyGXL with Prediction Algorithms to Determine to Vmin Working Voltage
Devices need to do Vmin test to find its minimum working voltage. For IP tests, we usually use the search method to find the Vmin points. It will take lots of test time. In order to reduce test time, designers implement machine learning in the test program. We collect PD(Process Detector) and Vmin data of thousands of devices first. Machine learning could find the relationship between these data, then give the predicted Vmin value of tested devices. We only need to test pass/fail under the predicted voltage, thus test time will be greatly reduced. The machine learning model is provided by the product designer in Python code. What the test engineer need to do is send the required PD data to python function, then get the predicted voltage, do the corresponding IP test. This paper will introduce how to implement this method in the test program. We use PyGXL to send data between the VBT program and the python program.
- How to do Vmin tests with prediction method
- Test flow introduction
- PyGXL usage in this case
- Trouble shooting
Best Utilization of Vector Memory Architecture on UltraPin2200
The semiconductor industry is facing a continuous increasing complexity in the integrated circuit design which has led to more challenges in testing. One of the major challenges is the increase in parallel and scan patterns size due to new manufacturing processes and device testing requirements. The improved capabilities and performance for UltraFLEXplus digital instruments UltraPin2200 and UltraPin2200+ addresses these challenges by providing larger and pooled vector memory shared across channels, larger scan capabilities, and more flexible memory allocation to increase pattern depth. With careful consideration in channel selection the vector memory capabilities can be further utilized beyond the spec and will demonstrate how the memory is consumed by scan and functional patterns. The objective of this paper is to explore the ways to maximize the vector memory utilization with the UltraPin2200 vector memory architecture and decipher the LicenseRequirements file and allow a user to calculate/predict the appropriate memory license for the application. The techniques discussed include channel assignment considerations during pre-design DIB stage, implementation of site copy feature, and functional vector compression which have been proven to improve memory consumption in several projects with large patterns.
Plan for a Successful Network Device Conversion from UltraFLEX to UltraFLEXplus
The UltraFLEXplus has been developed to provide many platform and instrumentation advancements. Leveraging these advancements for network switch devices, such as higher power supply density and digital vector memory enhancements, allows for increasing site count and therefore throughput. Successfully navigating the transition from UltraFLEX to UltraFLEXplus including increasing site count, requires thoughtful planning and knowledge of best practices which this paper aims to address. The information shared in this paper is based on a successful project conversion from UltraFLEX single site to UltraFLEXplus dual sites for a networking device. This will include a set of requirements to begin the conversion, suggested steps to follow for the conversion, typical challenges experienced and how to work through them or avoid them, as well as tips during hardware debug. The requirements consist of exactly what information you’ll need to have ready to start the process. Suggested steps will cover power supply selection and channel assignment, test program conversion, pattern conversion, and debug challenges.
Improving Memory Test Performance Using FLS
In traditional memory function test, failure data generated during pattern execution is stored in a specific space for failure analysis, and after the pattern is finished, it is analyzed through scanning processing. And to store the faildata generated during pattern execution, a physical space with a logical address proportional to the storage space of the device being tested is required. So, pattern execution time and faildata analysis time are required as time elements of the general test process, and a large amount of faildata storage space is required as space element. If the faildata can be checked and analyzed immediately while the pattern is running, we can finish analyzing the faildata of the pattern as soon as the pattern is finished. And real-time faildata can be checked and analyzed during pattern execution, so there is no need for a specific space with a logical address space. This paper explains FLS (Fail List Streaming) a new feature of the MAGNUM platform that can check and analyze fail data generated during pattern execution. Also, explanations of components used in FLS, FLS configuration, benefits, and how to use them will be covered.
RF/mmWave
High Volume Ultra Wideband Device Testing on the UltraFLEX
Ultra Wideband Testing on the UltraFLEX.
More and more RFID and Location “Tag” devices are adopting the Ultra Wideband Pulse Position Modulation techniques outlined in the ieee spec 802.15.4. These UWB-PPM radios are becoming popular in the consumer space and require cost-effective, high-volume production test solutions.
UWB-PPM radios operate in the 6-10.5Ghz range and have modulation bandwidths approaching 2 GHz. UWB-PPM radios typically have four (4) RF ports: one (1) TX port and 3 (3) RX ports. TX output power can be as high as +20dbm.
Typical TX tests include:
- TX Output Power
- TX Spectral Mask
- TX Pulse Accuracy
- TX Pulse Jitter and NMSE
- RX gain,
- RX PER
- Time of Flight,
- Angle of Arrival
Comparison of WIFI7 Test Solution On Teradyne Instruments
Wi-Fi 7, based on features defined in the IEEE P802.11 be draft amendment. Wi-Fi 7 enables significantly faster speeds by packing more data into each transmission. 320 MHz channels are twice the size of previous Wi-Fi generations. 4K QAM (Quadrature Amplitude Modulation) enables each signal to more densely embed greater amounts of data compared to the 1K QAM with Wi-Fi 6/6E, which – to continue the truck analogy-- is like having professional movers optimize truck cargo space to pack the maximum number of boxes.
How to address this Wi-Fi 7 320MHz channels band width and 4K QAM modulation / demodulation test challenges. Teradyne have LitePoint box solution and also new generation RF instrument - UltraWave 8G based on UltraFlexPlus Platform.
We had setup experiment with LitePoint box and UW8G for investigation. In this paper, we will compare test solution RF performance on EVM, ACLR etc, and also programming model and test time. It will help us understand advantage and disadvantage of each solution.
Moving Up? Meet UltraWave24G: An RF instrument for 6 to 24 GHz UltraFLEXplus Testing
This presentation will provide an overview of the new UltraWave24G RF instrument for the UltraFLEXplus (UFP) platform. The UltraWave24G RF instrument is a 32-port, 6 to 24 GHz, high dynamic range instrument available for the UltraFLEXplus. It has applications in wireless 5G, WiFi, and SatComm communications. External loopback data will highlight some of the key specifications, features, and developments. This will include continuous wave measurements, multi-toned source measurements, phase noise, EVM, and ACPR. For the single capture EVM measurement and the multi-capture ACPR examples, an 802.11be 320 MHz bandwidth 4096 QAM modulated waveform will be used.
This presentation will compare the UFP UltraWave24G to the UltraFLEX UltraWaveMX20 and will touch on the effort required to run an UltraWaveMX20 program on the UltraWave24G (not much!). After this presentation, the audience will have a preliminary understanding of the Ultrawave24G capabilities, the instrument architecture, its performance, and how it is differs from the UltraFLEX UltraWaveMX20.
You Asked For It and You Got It – the UltraWave8G! A Shiny, New RF Instrument for your 50 MHz to 8 GHz UltraFLEXplus Applications
For about ten years, the UltraWave24 sub-6 GHz RF instrument has been the RF workhouse of the UltraFlex platform. A few years later, the UltraWaveMX8 extension instrument was added, extending this range to 8 GHz. In 2023, by demand, the UltraWave8G was introduced as the first RF instrument on the UltraFlex Plus (UFP) platform. This single slot instrument has similar functionality to the UltraWave24 and MX8 combination plus several new features. This presentation will provide an overview of the UltraWave8G RF instrument for UltraFLEXplus. Loopback data will highlight some of the key specifications, features, and developments. This will include CW measurements, two-tone source with IMD suppression, phase noise, and a single capture 802.11be 320 MHz bandwidth 4096 QAM modulated signal both with and without native cross correlation. This presentation will compare the UFP UltraWave8G to the UltraFLEX UltraWave24 and UltraWaveMX8 combo and will touch on the effort required to run an existing UltraFLEX program on the UFP UltraWave8G (not much!).
After this presentation, the audience will have a preliminary understanding of what this instrument architecture, performance, and new features including native cross correlation.
Accelerated RF SOC Test Development Utilizing Modularized Simulation and Integration
To improve device hardware and software quality and decrease the TTM (time to market); test engineers are frequently required to develop test programs ahead of real device or related hardware being available with or without a tester. How to simulate a device and develop a high coverage test program in the condition of without a substantial DUT (Device Under Test), DIB (Device Interface Board), hardware connections or even a tester is becoming a growing challenge for almost all test engineers as well as the ATE industry.
This paper will introduce a novel method to simulate multiple complex RF SOC devices in one test program. Real hardware modules with a variety of applications have their independent software sub-program; they are the most basic blocks in this system. Through different combination of these modules, different scales and types of RF SOC devices are build up. At the same time an related integrated test program is auto generated.
To guarantee the coverage and complexity, the modules repository will include as many possible types as possible of modules ranged from: RF LNA, mixer, modulator, demodulator and so on. Each module may have its own protocols like JTAG, SPI; these can prove device interface as well. The test type in each sub-program will also cover as many possible test items.
Understanding and Testing Wi-Fi 7 On the UltraFLEXplus
Wi-Fi 7 is the next generation standard in WiFi technology. Wi-Fi 7 also known as Extremely High Throughput (EHT) or "802.11be WiFi” builds and improves on the current 802.11ax WiFi standard.
There are many challenges with test Wi-Fi 7 devices. The Frequency Range has been expanded up to 7.5GHz requiring ATE instruments to increase the upper end of their frequency range to cover
Wi-Fi 7 as well as doubling the information BW to 320MHz and incorporating Multi-Band/Multi Channel operation. The modulation scheme has been increase from 1024 QAM to 4096QAM.
This requires excellent phase noise of the Local Oscillators in the ATE instruments to measure these very aggressive modulation schemes. High bandwidth RF instruments are need to meas the 320MHz 801.11be signal.
This paper will describe the Wi-Fi 7 Standard. We will also provide detail descriptions of UFLEX Plus instruments UW8G and UW24G and use models for MiMo and SiSo testing Wi-Fi 7 on the UFLEX Plus platform.
Lessons Learned Developing An Early Adoption UW8G UltraFLEXplus Test Solution
The UltraWave8G is the first wireless instrument available exclusively on the UltraFlexplus platform. The UltraWave8G provides the functionality of the UltraWave24 as well as the UltraWaveMX8 wireless instruments available on the UltraFLEX platform with added features, enhanced bandwidths and frequency operating ranges.
The same wireless IG-XL logical instruments available with the UltraWave24 and UltraWaveMX8 are available with the UltraWave8G. Further, with few exceptions, the same logical instrument programming syntax supporting UltraWave24 and UltraWaveMX8 will support the UltraWave8G.
Likewise, most of the DCVS and DCVI syntax supported on the UltraFLEX with the UultraVI80 and UltraVS256 is supported on the UltraFlexPlus with the UltraVI264 and UltraVS256-HP. Further, the digital instrument syntax of the UltraPin1600 is largely supported on the UltraPin2200 available on the UltraFLEXplus; though UltraPin1600 supported pattern files must be recompiled to be supported on the UltraPin2200. Finally, the UltraFLEX syntax for programming the support board User Supplies and Utility Data Bits also is largely supported on UltraFLEXplus.
With compatibility of much of the UltraFLEX and UltraFLEXplus syntax and the adoption of the UltraFLEXplus ChannelMap syntax, much of a wireless test solution supported on the UltraFLEX can migrate to the UltraFLEXplus with limited modifications to the test program.
This paper will share some programming lessons learned optimizing an UltraFLEXplus wireless program adapted from an UltraFlex program to take advantage of architectural enhancements of the UltraFLEXplus enhancing throughput of the final solution.
Testing Radio Frequencies with .NET in IG-XL
Which programming language will you use to program the new UltraWave24G Instrument -- Teradyne's latest offering for MMW testing through 24GHz on UltraFLEXplus? VBA, VB.NET or C#? VBA continues to be a good choice, but as of IG-XL 10.40 on the UltraFLEX and UltraFLEXplus platforms, the ".NET Development in IG-XL" feature allows test engineers to program tests in VB.NET and C#. The demo program for the UW24G includes tests and DSP algorithms written in all 3 available languages: VBA, VB.NET and C#. We’ll use code from this demo program to compare and contrast the new .NET language options. We’ll review the Visual Studio IDE and it’s feature set.
The presentation will include detail on DSP routines written and running in .NET. This presentation will introduce RF test engineers to ".NET Development in IG-XL" for UltraFLEX and UltraFLEXplus platforms and focus on the benefits of using these modern languages for Test Engineering.
Signal-Table Making RF Testing More Efficient
IG-XL Signals are defined as a software entity representing RF, mixed signal or digital test stimulus, capture, setup, and control.
Compared to pin language, signal language will not affect hardware until the signal is applied with specific active commands like LSC (LoadSettingsConnect) , Start/Trigger, etc. There are many ways to organize and use the signals in the whole IGXL test flow, and you will find different ways will results in different test time.
To achieve reasonable test times while maximizing program development efficiency, users should understand difference between pin and signal language and use the advantage of signal features.
This paper will discuss and compare the different ways defining and utilizing signals and introduce a well proven signal-table-method. In this method all stimulus and capture Signals (RF, mix signals, DSSC etc.) are well organized in a table and preloaded only one time prior to the production run. Preloaded signals then will be shared by all the test instances, VBT functions and POP patterns. Multi-triggering or any POP bursting/combining can easily implemented with this method. Signals will be utilized and test time is minimized. In this paper, real cases with signal table will be demonstrated and test time benefits will be compared to traditional way.
Rapid RF/mm-wave Prototyping on the UltraFLEXplus
Getting new silicon designs up and running quickly on ATE testers is a key Time to Market concern. The ability to get prototyping and evaluation boards up and running on the tester to start design verification and test development is beneficial to meet tight release schedules. The UltraFLEXplus DIB interface is ideal for rapid prototyping of RF and mm-wave designs. The UltraFLEXplus has a suite of high density RF and MM wave instruments with fully compliant waveform generation and analysis tool to support existing and burgeoning communication standard like 5G/Wifi7 and UWB.
The UltraFLEXplus RF digital and DC instruments are code compatible with the UltraFLEX, so if a test engineer has a “tool box” for go to code for the UltraFLEX, it can be used on the UltraFLEXplus. This paper will go over the UltraFLEXplus DIB interface and rapid proto typing techniques used with the following instruments: UW8G, UW24G, UltraPin2200 (PA), UltraPac300, UltraVI264, UltraVS256.
A Look At The Next Generation of ATE To Test The Next Generation of Wireless Devices
5G smartphones and the wireless IC integration within are driving ATE complexity for more frequency, more bandwidth, and more site density (not to be confused with Moore’s Law in the digital domain). In response, UltraFLEXplus is our next generation RF solution that addresses these drivers for both characterization and production purposes. This introductory session will overview the 5G smartphone architecture and how our new RF instruments’ architectures, UltraWave8G & UltraWave24G, will satisfy these needs: UltraFLEXplus versus UltraFLEX. Focus is primarily on transceivers, including 5G-IF (not antenna in package modules). Session will span both technical and economical merits such that afterwards, attendees will have a broad understanding of our innovation and value proposition, respectively.
Advanced Wireless Solution for Characterization Activities
Teradyne’s new wireless approach also supports both banded and broadband configurations. In this session, we discuss the versatile reconfiguration for continuous frequency coverage that enables test for both in-band and out-of-band performance. In this way, our broadband configuration accelerates characterization while our banded configuration supports your optimal high volume manufacturing goals. This session will overview this versatile broadband architecture, describe the implementation, and present actual test data for our broadest configuration: 50 MHz to 24 GHz. Attendees will primarily takeaway how our banded modularity supports broadband test activities.
Antenna In Package Module Test Coverage
5G is synonymous with commercialization of mmWave technology, including the emergence of beamforming. This session will overview the antenna in package (AiP) module along with the best practices in test coverage from wafer sort to over-the-air (OTA). Moreover, we will overview low-cost and premium test strategies across both UltraFLEX and UltraFLEXplus platforms. The goal is to familiarize yourself with this strategic new mmWave module within latest 5G smartphones that enables mmWave connectivity. Attendees will learn more about mmWave technology and emerging test methods to support characterization and production so they can make better choices for their own test strategies.
Native Cross Correlation on the UltraFLEXplus UltraWave8G
This session presents a new native characterization method that reveals the true performance of your DUT by effectively removing the tester effect that potentially masks your results. As background, critical tests of ACLR and EVM are examples where removing these masking effects are desirable, but cumbersome to implement due to the inherent signal distribution prerequisites. Attendees already realize that every dB matters, so this session reveals this new native capability only available on UltraFLEXplus. Afterwards, attendees understand how this new tool can apply to their next new silicon ramp, with support for both characterization and production activities.
An Introduction of Automatic Probing System
Automatic probing system(APS) is a solution for mmWave DIB de-embedding which operates up to 53 GHz, and the purpose of this system is designed to help DIB DIAG application engineers quickly identify RF/Analog-related failures(such as the connectors, cables, switches/relays and PCB traces) at the NPI phase. This scalar version of de-embedding system also provides an efficient and reliable way to remove attenuation of input and output traces from the test fixture and increase fault coverage.
In summary, DIB de-embedding is essential to characterize RF devices accurately. Automatic probing system (APS) is an intuitive solution with plug-in tool in IGXL to assist application engineer to evaluate the impact of the load board on the signal quality and make necessary adjustments or compensations.
System Level Test
Optimizing the SLT Test Strategy: Interface Design and Test Execution for Efficient System-Level Testing
This paper delves into the optimization of the system-level test (SLT) strategy by focusing on two critical aspects: the interfaces between the system-level test board (SLTB) and the SLT tester, and the design and strategy for executing and sequencing tests. With the growing challenges posed by shrinking geometries and complex packaging in semiconductor testing, SLT has emerged as a crucial solution.
Efficient testing and future scalability heavily rely on the design of the SLTB interface. By capitalizing on the capabilities of the SLT tester, such as dual power supplies and high-speed serial interfaces like SPI, an abstract interface can be devised. This interface remains constant while the test requirements for Devices Under Test (DUTs) evolve. By employing a high-speed serial interface for testing, the SLTB can accommodate expanded input/output capabilities and integrate mock hardware using FPGA or supervisory test board processors. This design approach ensures consistent test interfaces, effectively optimizing the SLT test strategy regardless of device or DUT evolution.
The paper also explores test execution and sequencing, specifically focusing on two patterns: software based self-test (SBST) and tester-driven testing. Each approach presents trade-offs in terms of development time, test execution time, debuggability, and ease of making changes. Leveraging tools like Teradyne Test Executive empowers test engineers to easily write, sequence, and modify tests, enhancing flexibility and reducing development time. Conversely, SBST relies on specialized embedded resources, making test changes more challenging.
By thoughtfully considering the design of the SLTB interface and test execution, semiconductor manufacturers can optimize their SLT test strategy. This optimization leads to high-density manufacturing, efficient utilization of board space and features, and streamlined testing processes. These improvements enhance testing efficiency and flexibility, facilitating smoother transitions from bench-scale to high-volume manufacturing, and ultimately ensuring the production of high-quality integrated circuits.
High-Protocol Serial Scan for System Level Test: Challenges, Methods, and Integration
As the semiconductor industry continues to advance with smaller geometries and increased packaging complexity, testing these devices poses significant challenges. System level test (SLT) has emerged as a promising approach to address these challenges by enabling testing at a higher level of integration. This paper explores the use of high-protocol serial scan testing and discusses methods to overcome the associated challenges.
By leveraging standard protocols such as USB and PCIe, high-protocol serial scan testing offers cost-effectiveness and improved diagnostic capabilities. The paper highlights the benefits of SLT, the limitations of traditional scan methods, and the advantages of adopting high-protocol serial scan testing. It delves into the background of scan challenges, including limited pin count, increasing data volume, and advanced packaging constraints. The need for innovative solutions to ensure comprehensive scan testing in the era of chiplets and site count limitations in automated test equipment (ATE) is also addressed.
The paper categorizes scan testing into parallel scan and serial scan, emphasizing the growing trend towards serial scan adoption. Low-protocol serial scan reduces the number of required test pins, while high-protocol serial scan leverages commonly used mission mode protocols like USB and PCIe, enabling efficient and cost-effective testing.
Furthermore, the paper demonstrates the integration of high-protocol scan testing into SLT, showcasing its ability to test high-yield patterns at a lower cost of quality compared to traditional methods. The scalability and flexibility of SLT systems allow for parallel execution of high-protocol scan tests, enhancing overall test efficiency. Additionally, the seamless transition between ATE and SLT facilitates easy debugging and yield improvements. The scope of high-protocol serial scan testing extends throughout the lifecycle of a chip, encompassing wafer sort, final test, SLT, and in-field testing.
Adapting Atlas SLT Software to Customer Processes and Hardware Platforms
Atlas SLT is the new software environment for the Teradyne SLT Systems. This environment provides umbrella support for a variety of use cases, including test program development, system operation in production, and system support. However, Atlas SLT is not only designed to provide a great user experience, but also to be easily adaptable to both different customers and different hardware platforms.
This paper will start by describing basic capabilities of the Atlas SLT software environment, and then focus on the techniques employed to make this environment flexible and adaptable. Specifically, it will describe the mechanisms for supporting variations in:
- customer production processes
- customer validation rules
- bin mapping
- test development options
- test execution specifics
- test result reporting options (a.k.a. datalogging)
- custom procedure support at start lot, end lot, start test and end test
- and several other areas.
PortBridge Helps Provide a Common Toolset and Use Model for ATE and SLT Test
System-on-Chip (SOC) device designs are becoming increasingly more complex. The connections between the multiple IP blocks are difficult to test during ATE package test without significantly increasing the overall test time. System Level Test (SLT) provides a practical, economical solution to this problem. The Titan solution is robust, but it does introduce a new programing model and user interface. Our customers have requested tools and interfaces that are similar to products that currently exist in IG-XL for the UltraFLEX family of products. We have developed platform agnostic tools and interfaces to meet this demand. These include our new High Speed Serial Scan Debug tool and support for PortBridge interfaces on Titan. These components allow us to share tests and debug environments across both systems. This enhances both platforms while reducing the overall learning curve for migrating from one system to the other.
High Speed Protocol/Phy Testing
High-Speed Serdes Channel Design Process for First-time DIB Success
As the advanced digital ASICs increase their complexity and transistor count, there is an ever increasing need to move vast amount of digital information into and out of the DUTs. Outside DRAM, chip-to-chip communication happens predominantly over high-speed serial interfaces. Their data rates are ranging from 8Gbps NRZ to 112Gbps PAM4 per lane. The broadband frequency components in the serial signals span continuously from low RF range well into the microwave range. The corresponding serial signals travel over the long and complex channel topology from the instrument PE to DUT, compared to conventional on-DIB simple loopback path. Good signal integrity is crucial for ATE solution success.
This work summarizes the design process and signal integrity considerations for general high-speed serial instruments and their DIBs, focusing on the channel design and system-level validation. We are using the first UltraFLEXPlus serial instrument DIB, namely scope jack DIB, as the sample. It is a general-purpose text fixture that can work with multiple high-speed serial instruments. The DIB design has achieved one-spin success during the US20G Image Sensor PHY validation and prototyping. The overall end-to-end channel, including the instrument board and the scope jack DIB, achieved less than 1e-15 BER under a calibrated stressed eye at 20Gbps. The same design techniques and validation methodology are also applicable to other high-speed serial boards in general.
New Solution for 112G PAM4 PHY Loadboard Design
Nowadays, we meet new challenge in loadboard design for PHY Chip: 112Gbps high speed, up to 8 lanes TX-RX loopbacks with 0.1uf cap, 0.5mm BGA pitch. Usually, it will need 3-5 layers to route the loopback, do length match and add the isolation via. As a result, the board fabrication risk is getting much higher, and also,the tight SI spec is getting much harder to meet.
In this paper, two traditional solutions have been verified. The first one is PTH via backdrill solution, it can be used when BGA is 0.8mm pitch or larger, it can help easily pass the simulation spec, however, it is not suitable for pitch with 0.5mm or smaller, because there is no enough space to do signal optimization, which leads to bad return loss and crosstalk. The second one is Blind via solution, as blind via has no stub, it can help to get good simulation result, however, it will need more than 3 types of blind via, which will increases 80% board fabrication risk and the board yield will be very low.
To overcome this dilemma, a new solution combining the advantage of above two solutions is proposed, it is laservia+PTH backdrill solution. With the help of laser via, it allow us to route the loopback in outer ring of BGA in 1 layer, so that to other loopback in inner ring, we can easily do fanout use PTH via, and then backdrill the via stub. In this case, there will be larger space to do signal optimization, which will guarantee the impedance of whole signal path to be controlled within 10% tolerance.
As BGA fanout vias should be filled with epoxy, to be more serious, in this paper, the effect of air over stub and epoxy over stub after backdrill is also discussed. It is verified that air over stub hardly leaks the energy away, it will have better insertion and return loss, which means we should apply epoxy filling first, back-drill last.
The final result shows we get good signal performance (0-28Ghz, Insertion loss=-4.27dB, Return Loss=-12.14dB, Power-Sum crosstalk=-40dB) and low board fabrication risk, and also the board lead time can be reduced by 40%.
Characterizing MIPI Loopback Path Optimization and Lessons Learned for CPHY & DPHY Test
MIPI CPHY/DPHY is fundamentally different from typical single-ended or differential IOs, it is posing challenges to both ATE and SLT testing. A common test strategy adopted by most chip makers is Loopback, however, the loopback scenarios can be very complex.
In this paper, the author will introduce the challenges of MIPI CPHY & DPHY Test with an example of complexed Loopback scenarios. Performance characterization was performed on two major switch choices: high performance mechanical relays vs. high bandwidth CMOS MUX ICs. The study also covers other aspects such as cost and real estate.
The second goal of the paper is to discuss the lessons learnt during optimizing the high-speed loopback path on the DIB, specifically how to optimize the vias, which is the major bottleneck of the channel performance during a high-speed PCB design.
UltraPort-PCIe: Native PHY Testing to Improve Coverage and Reduce Test Cost
Moving test coverage upstream has long been a desire to reduce test cost and catch failures earlier in the production flow. Complex PHY protocols and the desire to run mission mode tests on the DUT make it difficult to create coverage-equal functional patterns, or traditional ATE tests from SLT coverage. The new Teradyne UltraPort-PCIe and UltraPort-USB instruments allow the user to run high protocol scan while also providing a Linux environment where the user can natively run apps and scripts to exercise the PHY and the DUT in an SLT like environment on the UltraFLEXplus. Adding native PCIe and USB to your ATE test flow can enable failures to be caught as early as wafer sort, allowing failures to be fed back to the fab earlier and saving the cost of building the die into a packaged part and additional insertions.
Advanced Simulation and Measurement Correlation Methods for Over 100 Gbps PAM4 High-Speed Design
High-speed signal channels are essential in Teradyne’s high performance ATE systems. Base band signal delivery at 100 Gbps and higher data rate is unavoidable challenge Teradyne and its customers have to solve. To ensure high design quality and satisfactory design specifications, simulation and measurement correlation are critical. However, it is much harder to achieve a good correlation between simulation and measurement for any system with a speed over 100 Gbps.
In this work, we focus on the design of OLT(Optical Line Termination) device that needs 100 Gbps PAM4 and even higher signal delivery high-speed links board designs. To achieve this objective, critical issues affecting design specifications, simulation accuracy, measurement reliability, and correlation discrepancies are discussed. For the 100 Gbps board, design optimization by simulation takes majority time in the design process. Many details need to be investigated to achieve a collectively good performance. In the other hand, during the measurement stage, probe selections and calibration must be carefully planned. However, it was rarely discussed how to achieve the correlations between measurement and simulation in literatures. In this work, we will present our successful 100 Gbps benchmarks and critical concerns behind their simulation, optimization, and measurement correlations. All detailed factors such as simulation port setups, boundary definitions, hardware selections, calibration methods, measurement setups, and result expectations are included in the presentation. Great correlations for multiple channels in both frequency (VNA) and time domains (TDR) have been achieved. It serves as good references for challenging 100 Gbps or higher high-speed board designs. This work attracted high attentions and good feedback from some Teradyne’s new customers.
An Integrated Solution for 5-112Gbps PAM4 and NRZ PHY Layer High Volume Production Test with Lab Quality
As a follow up to the 2022 TUGx paper demonstrating a DIB based 112Gbps Phy test solution, this paper will present a fully integrated solution with extended performance as a regular testhead instrument. With innovations in signal delivery architecture, instrument capability and modular implementation the new solution provides a simpler, more efficient, more reliable and leverageable solution for the UltraFLEXplus platform.
Network processors, infrastructure networking, and backbone IT data farms continue to lead the charge applying FEC encoding and active equalization to PAM and NRZ SERDES channels to achieve the next round of step function improvements for data rates at 56Gbps, 112Gbps and even >200Gbps over single channel copper. Automotive, imaging, and consumer are not far behind. With such new technology, the industry is demanding some kind of ATE based test capability.
This paper will present measured results of an integrated instrument leveraging third party hardware combined with innovative software and signal delivery to provide lab quality measurement capability.
Silicon Photonics and Copackaged EIC and OIC: When is it Coming? How will it Impact SOC Test? Is Wave-Particle Duality a Thing or Just a Paradox? Can Heisenberg Test His DUT with Certainty?
Many network processors and high speed data interfaces provide low cost, low power implementations of electrical data interfaces running at 100’s of Gbps. Inherent to the scheme is signal degradation expressed in loss per inch; 0.5dB loss per centimeter for a 20cm coaxial cable may be acceptable but scaled up to carry data across a ¼ km of disk farm is a non-starter. The loss solution is fiber and optics. Optical loss may be 0.5dB per kilometer rather than per cm with a potentially much higher immunity to noise and interference.
New work has introduced fabrication technology that allows for silicon based lasers and optical components promising a shared monolithic die combining EICs (“Electrical ICs”) with OICs (“Optical ICs.”) Also promising are increasingly economic packaging approaches to building multi-die modules compose of both EICs and OICs. This paper will discuss the test challenges this presents for the usual SOC test flow and how these challenges are expected to emerge over time.
Hot Topics
A ChatBot for MyInfo
With the recent release of AI-based Chatbots like ChatGPT, the search bar has become an obsolete artifact of bygone times. It is now possible to have a conversation with a chatbot and to receive a concise summary of several relevant source documents for further detail.
While ChatGPT is a useful tool for general questions and answers, it falls short when it comes to providing specialized knowledge, such as in the field of Automated Test Equipment (ATE) testing. ChatGPT has been observed to provide inaccurate information or to fill knowledge gaps with fabricated answers (sometimes called “hallucinations”), which makes it an unreliable source of information. Teradyne is currently developing a chatbot interface to MyInfo. To ameliorate these issues, Teradyne is employing specialized techniques including indexing, vector search methods, prompt engineering, and model fine tuning to ensure reliable results.
There is a critical secondary requirement when we use chatbots for work – security. We must ensure that our company IP, as well as our customer’s IP, is not inadvertently released out into the wild. The chatbot landscape has finally matured to the point that Teradyne’s strict security requirements can be met, not only as described above, but additionally by isolating each customer’s IP from other customers and even with restricting Teradyne Applications and Field Service support to only those authorized for that specific customer account.
Teradyne’s chatbot interface to MyInfo will support Test Engineers in their search for specialized knowledge of Teradyne’s tester.
Designing for Maximum Throughput When Converting to ETS-800
There are many devices running on ETS-300, ETS-364 or ETS-88 that may have much better economics when converted to an ETS-800 solution. The advantages of the ETS-800 goes well beyond just giving the user the ability to scale to higher site counts. This presentation will cover some topics and share tips that can be helpful when making this transition. We will discuss items such as sample configurations, including suggested use of APEx. This will be demonstrated with detailed config block diagrams that show all tester resources mapped to device pins and DIB hardware. This will cover tester resource assignment, and planning of resource sharing. This will include a comparison of tester resources between platforms, and how to best utilize the latest instruments to provide the best cost of test. There will be a focus on hardware design, to make the best use of the Multi-sector technology built into ETS-800 MST.
How to Handle Massive Datalog Test Tracker Generation and Updates with Audit via iLogTracker
With the growing testing complexity and coverage, the project team handle increasingly vast amounts of test data (>20K datalog lines) and working with larger project team (>20 Apps). There are challenges and complexity with direct Test Tracker generation, accurate Test Tracker updates, and large project team coordination on weekly Test Tracker updates. Inefficient handling of complexity may lead to delays, errors, and decreased productivity.
To address the challenges of navigating the intricacy when managing the quality of test program development and tracking an extensive conversion project. This presentation will introduce a solution, namely iLogTracker (intelligent Datalog Tracker). The tool has the ability to read STDF file directly and generate Test Tracker with a click of a button. It automates the subsequent progress tracking by including a datalog audit report as an initial step to ensure the quality of the test program. Additionally, it offers an alternative solution to manage the Test Tracker at customer sites where file access is restricted.
This tool aims to simplify the progress tracking update process, optimize team collaboration, and enhance overall efficiency and effectiveness of large-scale projects.
A New Flexible Updated Production Control OI Using .NET
Production Interface is used in production line for all customers, each customer will develop their own customized OI based on different needs or setup.
For easier development of OI tools, Teradyne provides a control library named “ProductionControls.ocx” which was developed by VB6 more than 20 years ago. From time to time, customers are requiring an easier and more modern way of OI development, especially the VB6 development environment is not supported by latest OS. Therefore, we developed a new OI Controls library based on .NET(WPF), which is very flexible to create customized interface by dragging built-in controls even you don’t need to write any codes. At the same time, the new .NET Production Controls Library provides plenty of APIs to support fully control of test program execution, including the control drivers.
Here are the main topics of this paper:
- .NET Sample Production Interface
- Built-In Controls of .NET Production Controls library
- APIs provided by .NET Production Controls library
- Demo of how to create a Production Interface with .NET OI Controls library
Introducing the HSD-64 for the ETS-800
The HSD-64 is the next generation digital instrument for the mixed-signal ETS-800. This paper, published prior to the instrument release (target fall of 2024), aims to provide a preview. With doubled channel density, the HSD-64 enables higher site count and lower cost of test. Many feature enhancements are offered over the legacy HSD-32; including deeper memory, DSSC use model improvements, DIB Access, and others. These features benefit a variety of industry segments like Mobile Power, Automotive SoCs, Motor Controllers, and Power Management Devices. Compatibility has been a major topic in recent product releases; MST-2024A and the HSD-64 are no different. Considerable hardware and software efforts have gone into an emulation mode. Emulation mode significantly reduces the user effort when converting existing apps from HSD-32 to HSD-64. This paper will provide an overview of the features. It will also discuss the updated use models for DIB Access, DSSC, and Emulation Mode.
Teradyne Result Viewer (TRV) & Graphical Flow Results Applications
This TUG paper will discuss two applications: Teradyne Result Viewer (TRV) & Graphical Flow Results.
Teradyne Result Viewer (TRV): A newly developed application, which is a Data Application Server (DAS) that receives data from a tester through Tester Event Messaging for Semiconductors (TEMS) protocol. With TEMS protocol, TRV can run locally on the tester, or remotely on another PC. TRV allows user to view test results real time while test program is running. TRV performs statistical data analysis (CPK values, Standard Deviation, etc.) on the fly when new test results come in. TRV shows data in tabular form, which supports filtering, sorting, grouping, etc. User can also view the data with different type of charts (test result trend chart, histogram and boxplot). TRV supports exporting test result data to csv files, so user can perform result analysis later.TRV also displays real time binning and yield information, which supports tabular view for hard and soft bins, per site yield and overall yield. User can also view binning distribution, per site yield with pareto charts.TRV will be an useful tool for test/product engineers, such as troubleshooting test/product issues by utilizing statistical data and charts.
Graphical Flow Results: The new requirements and UI for graphically showing test results in IG-XL for debug runs will be described. The goal is to enable the test engineer to quickly identify and debug failing tests and sites. Test rows on the flow table will be colored red or green to indicate if the test passed or failed. The sheet selector will have a new tab that shows a hierarchical view of the flow tables that are also colored red or green based on the status of the tests on each sheet.
The sheet selector will also have a site selector that lets the user see which tests failed by site(s). Test program navigation from the sheet selector will be enhanced to quickly jump to and navigate between failing tests.
Minimizing the Time to Impactful Smart Manufacturing: A Platform Approach to Data Analytics
Semiconductor manufacturers continuously seek to improve device quality, production uptime, yield performance and factory optimization. Most current smart manufacturing solutions are applications focused on solving one problem for one use case. Deploying multiple point solutions creates challenges due to the difficulty and cost to develop, deploy and maintain these applications, and the inevitable reliability issues that arise due to poor integration. A platform approach to data analytics and smart manufacturing enables manufacturers to develop a diverse set of solutions on a single platform.
This presentation will introduce Teradyne Analytic Management Platform (AMP) which include:
- General interface of data source and action controller
- Common language in easy-to-use development environment
- Platform infrastructure for real-time data processing capabilities
- Smart manufacturing and data analytics solutions examples based on the platform like fleet management, test cell health monitor, smart power saving, test result analysis etc. will be introduced
- The system enables manufacturers to achieve data-driven insights and impactful results that positively affect reliability, uptime, yield, and factory floor utilization
Intro to Git for Test Engineers
This presentation is part of Teradyne’s DevOps effort and highlights the benefits of using the DevOps tools. It also introduces a proposed training path.
DevOps is a culture, practice, and set of tools that aims to unify the development (Dev) and operations (Ops) of software applications. DevOps enables teams to collaborate better, deliver faster, and improve quality and reliability of their products. To that end, Teradyne has developed tooling to support Continuous Integration (CI) and Continuous Delivery (CD). One of the cornerstones of collaborating on software development is effective workflows using a Distributed Version Control System (DVCS), namely Git. Before a team can implement DevOps using CI/CD, they first have to learn how to collaborate using Git.
Good technology comes from great teams! To enable the Test Engineer to learn Git, learn collaborative workflows, and prepare for DevOps, Teradyne developed a new training course, Git For Teams (G4T), based upon a book by Emma Westby by the same name. The course is comprised of three sections. Part I speaks to the stakeholders and focuses on working in teams, governance, branching strategies, and workflows. Part II communicates to the developers and concentrates on applying commands to the workflow. Part III deals with Git Hosting and Git Hosting Services. At the conclusion of this course, the student is prepared to use Git, working as a collaborative team member, and is prepared for the DevOps For Test (D4T) training course.
Improving ETS-800 Test Program Debug
The debug process of test programs may require repeated status reviews of instrument settings or measurement values. This is commonly achieved by the separate eRaide tool, but switching between that and the Visual Studio environment can affect the efficiency of the debug process.
RTDebugTools were developed to improve that process. They seamlessly integrate with Visual Studio, enhancing the efficiency of debugging ETS-800 test programs. They offer real-time updates of tester instrument status and alarms whenever a breakpoint is hit or code execution stops. This eliminates the need for manual updates and ensures instant access to accurate information. Developers can closely monitor and analyze instrument behavior, quickly identifying and resolving issues. With its streamlined integration and real-time updates, RTDebugTools optimizes the debugging process, saving time and increasing productivity.
This presentation will highlight the available features and demonstrate the workflow on typical debug scenarios.
Improving QMS Short Term Measurement Accuracy by Implementing a Spot Calibration
Battery Management Systems (BMS) using next generation Li-Ion battery chemistries such as LFP (LiFePO4) have a lower maximum cell voltage 3.6V vs. ≥4.2V and ~100mV SOC (State of Charge) drop from 80% - 20% vs. other Li-ion chemistries SOC drops ranging from 250 -280mV.
The more accurate the cell voltage measurement; the more reliable and repeatable the “State of Charge” (SOC) , “State of Health” (SOH), or in the case of an Electric Vehicle “Distance to Empty” (DTE) become. This has pushed differential BMS cell voltage measurement accuracy requirements down from ±100uV to ±50uV.
The QMS has excellent resolution and accuracy but needs to be tighter over time and temperature to meet future BMS test requirements. Spot Calibration (Spot Cal) requires monitoring Ambient Temperature (using QMS Air Temperature or a DIB Temperature Sensor) and / or the drift of a high precision voltage reference. During Spot Cal the Keysight 3458A DMM and the QMS both measure the same precision voltage reference.
The delta between the 3458A and QMS measured values is used to offset (Spot Cal) the QMS for any drift cause by temperature or time.
This presentation will detail the temperature response data measured while the QMS is cycled in a temperature chamber from 25°C +5°C and -5°C; with and without the use of a Spot Calibration.
The implementation of the Spot Cal procedure enables the QMS to meet BMS’s required +/-50uV short term measurement accuracy.
Showtool Not Only a Powerful Debug Tool – A Case Study in Which it Helped Reduce Test Time _4OCT
With more demanding requirements on test program development projects, for example, the competitive Cost of Time (COT) target which can potentially break into new markets, Test Time Reduction (TTR) plays an important role in this step.
In order to take advantage of Adaptive Pin Expansion Architecture (APEx) and floating architecture of ETS-800 tester, Showtool comes as handy tool to test program developers on ETS-800 system.
Showtool is a graphical tool that shows the status of all the instruments connections in ETS-800 system and how each connection path has changed at different sections of test code. Considering that ETS-800 tester is designed to allow flexibility in terms of instruments connectivity, users can use Showtool to understand what options they have to optimize connections and instrument setups, which often helps to reduce test time significantly.
This paper will go through how to incorporate Showtool into MST for debugging and the tips to use it for TTR with real case study in detail.
Managing Test Library Integration with Git Submodules
Effective test program development relies heavily on the reuse of existing and verified code, typically organized in separate libraries linked to the main program. Git Submodules, a powerful feature of Git, provide a solution for incorporating external repositories into a main repository while ensuring secure dependency management and version tracking. This paper presents a way of utilizing Git Submodules to integrate code libraries into a test program. The modular structure offered by submodules enables independent development and versioning of each individual submodule. Furthermore, the paper introduces Visual Studio Code as an ideal tool for managing Git repositories, as it provides intuitive integration also for Git Submodules. Its user-friendly interface streamlines the process of working with submodules, offering a convenient and efficient workflow. By adopting Git Submodules and leveraging the capabilities of Visual Studio Code, test program developers can optimize code reuse, simplify dependency management, and enhance collaboration within their projects. This paper is intended to be a basic guideline for developers starting to use Git Submodules in their test program development processes.
Unit Testing in IG-XL
Test Programs have come a long way from simple scripts only checking a handful of device parameters to todays large and complex software solutions. Creating and maintaining these is close to impossible without modular design concepts and the use of library code. The software industry recognizes the power of unit testing to validate functionality of shared components separately from their target environment. Focusing on small & granular code units allows for broader test coverage, better access to corner cases and more efficient localization of defects. As a side effect of the isolation however, the code may not have access to infrastructure it requires, so that must be taken care of.
With “.NET Development in IG-XL”, a wealth of support for software testing becomes available to test programs. This presentation explains the concept of unit testing in the context of .NET based IG-XL test code, it discusses several strategies for efficient implementation and proposes ways to interact with the IG-XL API where that is required.
Introducing IG-Correlate for Advanced Correlation Data Analysis and Reporting
Correlation data analysis can identify key problems in overall test strategy or implementation. With the introduction of TEMS and Teradyne Results Viewer (TRV), using statistical data analysis to monitor test program quality and stability during test program development/debug has never been easier. No more “eyeballing” datalog to look at the effects of a change! IG-Correlate introduces even more insight into your correlation data while you're still in the engineering lab. It uses collected data and optional reference data (imported from TRV or STDF) and analysis configuration information - including correlation targets and weights - to evaluate and score collected data against specified targets. This allows a Test Engineer to focus in on key problem areas, look for patterns, and execute experiments to investigate or fix unstable tests. IG-Correlate offers .NET and command line APIs to enable automation and offers an Oasis GUI to set up correlation targets and display overall score history. IG-Correlate can be used with IG-Review to generate customizable correlation reports. IG-Correlate’s correlation analysis scores can also be used for decision-making purposes in larger optimization automations.
DevOps For Test
In today’s ever-growing size and complexity of semiconductor device test programs, development teams need to utilize the best tools and methodologies to maximize productivity and collaboration. We will explore a new modernized test program development workflow called DevOps for Test(D4T) that uses Continuous Integration/Continuous Deployment (CI/CD) principles with standard tools and best practices from the software development industry to deliver high quality test programs. The D4T workflow uses the popular source control management (SCM) tool Git to help track, audit, and manage the delivery of high-quality test programs to the production floor. The next critical piece for any CI/CD system is to use an automation server like Jenkins to have it automatically run a D4T pipeline to verify that an IG-XL test program can pass the build, audit, test program execution, and data analyzer stages. How often does the pipeline run? Every time any user makes a Git push, which is exactly the meaning of CI/CD the software is always being verified! The configuration for the pipeline is done via the D4T App which will help team integrators configure all the necessary Oasis tools, D4T analyzers, and automation agents. In addition, the D4T app provides example pipeline scripts to get teams up and running quickly so that they can start their journey with the new D4T workflow, which will improve team efficiency and delivery high quality test programs.
Edge Inference and Maching Learning for Semiconductor Manufacturing and Test
IC Test is a critical part of semiconductor manufacturing and proper die binning has an important impact on the overall yield, product quality, process monitoring, and failure mode diagnostics. Edge analytics are becoming an increasingly important aspect of die disposition. By intercepting parts in real-time at wafer sort or final test, we can save downstream processing needs and improve product quality by predicting failures earlier, or before the parts are shipped. Furthermore, a complete MLOps platform to train, deploy, validate, and monitor a multitude of machine learning models across chip products is needed to achieve production worthiness. In this paper we will showcase a complete MLOps solution to realize improvement in identification and binning of failed parts compared to conventional statistical screening methods, among other use cases. We also show that by incorporating known cost data, we can automatically guide users to optimally tune the model for maximal failure capture with minimal overkill and realize significant business savings.
Power Device and Module Testing
Advanced ETS-800 Digital and Analog Test Time Reduction Techniques
Using some more advanced concepts on the ETS-800, the team intends to show means for saving test time on large user-based functions. The digital focus includes using dynamic storage of C++ vector maps with the waveform sheet of the DSSC to save test time when a repetitive large scale register map read is needed. Furthermore on the Analog side we will cover the advantage of using the per pin APU-32 AWG Pattern Generators to implement separate pattern based power cycling sequences for multiple supply pins. Finally we will show how we used instrument specific stat calls to create subroutines based on instrument states such that to avoid redundant API calls and thereby save test time.
Filtering Out Noise from Isolated DC-DC Converters in Test Applications
This paper presents an optimization method to filter out the noise from an isolated DC-DC converter in order to prevent the effect on small-signal measuring circuits. In general, there are many high voltage applications that require galvanic isolation for a power supply to provide power to different electrical components, thereby protecting sensitive circuits from high voltage spikes, safety and floating ground requirements. But all isolated DC-DC converters have switching devices that generate noise. The noise is mainly common mode noise. It will be transmitted from input (primary) to output (secondary) by coupling capacitance within the converter, then the output waveform captured will be overlapped with ripple (probably hundreds of KHz switching frequency) and high-frequency noise (up to 20MHz) which will affect the measuring accuracy. The proposed method here is intended to provide a reference in your future designs and eliminate the effects from an isolated DC-DC converter.
Fast Dynamic RDSON
Manufacturing of GaN power transistors is still a challenge. They sometimes show undesirable characteristics and need to be screened out. An example is the current collapse effect - dynamic RDSON. A Dynamic RDSON test can be included in the test list for GaN power devices. This test will be done by doing several RDSON measurements (at least 2) with a stress voltage pulse between the first and the second measurements (pre- and post measurements).
This paper will provide an overview of the GaN discrete power device with its characteristics and also describe the dynamic RDSON test method, its test setup with parameters and discuss the challenges in implementing this method. The test method was developed on an ETS88-DUO-TH but the basic concept can be applied to any test platform that has the capability to provide the required current and switching speed.
An Introduction of Test Concepts for Power Discrete Devices Pertaining to “Known Good Die” Testing
New environmental regulations to reduce average CO2 emissions and automotive trends have accelerated the deployment of electric vehicles and hybrid electric vehicles. As one of the key components of power converters and inverters, power modules demand is growing rapidly. Due to high vehicle safety standards and harsh environments, automotive power modules often have stricter requirements on power efficiency, robustness, reliability, weight, volume, and cost than industrial products.
One power module normally packs multiple power discrete chips to get higher power density with smaller size. The quality of each chip directly affects the reliability of the module. To increase the reliability and lower the module packing cost, more test requirements are added to power discrete wafer prober test and some manufacturers have started to do KGD (Known Good Die) test for more test coverage.
This paper will introduce power discrete KGD test concepts, talk about the difference between wafer prober test and KGD test, power discrete KGD test challenges and Teradyne solutions to address different test requirements.
A Comprehensive Solution to Test 32 Sites Power MOSFET Wafer on the ETS88DUO
High power discrete devices are commonly used in various applications, such as power electronics and energy storage systems. A key part is the MOSFET which plays an important role.
Testing these devices at the system level can be challenging due to the complexity of the hardware and the required high voltage isolation.
Different resources would be used in MOSFET testing, such as a 3KV power source and/or 1000A current source. The ETS88D is a good choice to integrate these types of resources.
Even an ETS88D has some limitation - it could not be used for direct docking to a handler or prober, therefore we would design cables for this solution.
In this paper, we discuss a comprehensive solution to test 32 sites power MOSFET wafer on the ETS88D. The framework includes the design and implementation of a DIB and module board layout, the selection and use of cables, stiffeners, and mechanical parts, as well as the consideration of safety measures and isolation techniques.
This solution not only covers existing or common test items, but can also be defined by customers themselves for some special testing, which can be realized on the customized board.
The Power MOSFET Wafer Test Solution provides a reliable and efficient method for testing high power discrete devices at the system level and can be useful for researchers and engineers in the field of power electronics and energy storage systems.
LTspice Simulation Skills for Test Engineers
In semiconductor device test applications, an excellent test solution is usually based on very accurate signal and test circuit description, sometimes a complex circuit requires a lot of circuit analysis and prototyping efforts in the test method design phase. Test engineers who can effectively use circuit simulation not only can obtain a powerful DIB circuit describing tool, but also can quickly complete design verification and shorten project lead time. Thanks to the powerful, flexible, and free LTspice tool provided by Analog Devices Incorporated, this article recommends LTspice as a daily tool for test engineers and introduces the simulation skills for using LTspice.
This paper proposes that effective simulation should focus on modeling problems with the most simplified circuit to understand the circuit behaviors, rather than expecting to get the simulation results closest to the actual circuit responds. Therefore, an example of using a simple circuit to model the maximum operating time of a pulsed V/I source in high current testing is provided. Finally, the common applications related to signal bandwidth and transmission line in DIB circuit design are used to demonstrate the features of LTspice in solving such problems. These examples serve as a starting point for test engineers to better use the LTspice.
ETS-800 I2C Protocol Test Time Reduction
This paper looks at how to reduce digital communication test time by saving any I2C communications uploaded from the PC to the Tester in a unique memory label location on the HSD. On the next test run the saved communication does not need to be reloaded to the tester. The saved label is called instead. With this technique the write time is completely eliminated.
This paper presents work being implemented on a customer project that has ~3,000 I2C communications per test run. The communication protocol which is being implemented utilizes the DSSC START, CONTINUE and STOP ENGINES to merge multiple writes together. But even with this test time savings the amount of overhead caused by uploading DSSC data thousands of times with the dsscwrite command is still extremely significant and detrimentally impacting to the customer’s test time budget.
Automated DIB Diagnostic Tool
DIB diagnostics is often required by customers to be implemented as part of the testing solution that Teradyne provides. One of the most common components used to configure each test into the test flow world, is the mechanical relay. Therefore, an automated way to develop diagnostics for these components will be truly helpful to reduce development time and potential human errors during this phase of the project. The paper proposes an automated method that takes the schematics of the whole test solution to generate the diagnostic code in C++ as much as possible for the mechanical relays present in the design. This tool is being used successfully in a leading power semiconductor company testing with an Eagle System. The debugging process consumed twice as much time before having this tool working. It is also deployed in a project with MOSFET devices on the ETS-88 platform helping engineers to get faster diagnostic of damaged relays
TRU2.0 Introduction
Power devices such as MOSFETs and IGBTs are widely used in power supplies, motors, and inverters. Measuring transient thermal resistance is one of key factors to ensure the manufacturing quality of power devices. The Thermal Resistance Unit (TRU2.0) provides variety of transient thermal resistance testing methods for discrete power devices such as MOSFETs, IGBTs, and DIODEs. The TRU2.0 is enhanced from previous version to support SiC N-Channel MOSFET and Enhanced-mode GaN HEMT with programmable gate-off voltage and wide measurement range for dVSD.
This presentation will provide an overview of the TRU2.0 and its programming techniques with measurement examples.
Production Solutions
Test Time Analysis on UltraFLEXplus: Execution Profile vs. Timelines
When collecting test time data on the UltraFLEXplus, users may immediately think of using Execution Profile feature in IG-XL. However, depending on which column of time data you observe and how the tests are programmed, the data could possibly be misleading. This is due to the PACE asynchronous architecture of the UltraFLEXplus tester. In some cases, the VBT time of one test may be artificially inflated due to a command in a previous test. In this paper, the author detail a use case where this misalignment occurs in the Execution Profile and explain why this happens.
This paper will also discuss how this can be avoided by viewing the data in Timelines. The author will briefly discuss the benefits of using Timelines to view test time data on the UltraFLEXplus tester. Benefits include the graphical representation of test time in a horizontal view, highlighting efficient pipeline usage, identifying gaps and potential test time savings and comparing two sets of data easily. All of these features, and the aforementioned misalignment of actual time on the Execution Profile, are reasons why users should strongly consider using Timelines to view UltraFLEXplus test time data.
Enabling Adaptive Test Strategies: Shifting to an Improved Development Platform for Data Analytics
To improve yield and test efficiency, semiconductor manufacturers seek adaptive test strategies that allow predicting the behavior of a device-under-test (DUT) based on statistical data analysis and support triggering focused testing. To provide this, test engineers need a set of pragmatic solutions to process test cell data and act on it in a way that is reliable, portable, expandable and low cost. They need the flexibility of choosing between turn-key solutions and a development platform to create customized solutions. Teradyne is introducing a new Analytic Management Platform (AMP) which provides a platform approach to data analytics by enabling development of a diverse set of portable solutions. This presentation will give an overview of the AMP platform infrastructure focusing on its real-time data processing capabilities and its general interface for streaming data and requesting actions. We will describe how the Software Development Kit for AMP can be used to analyze test cell data and to control aspects of the test cell. The AMP SDK expands upon the benefits of the Tester Events Messaging Standard (TEMS) by adding the powerful bidirectional ability required to control the test program. The custom solutions built with the AMP SDK can easily be run outside the tester host computer, either on an external server or on the new UltraEDGE computer, to avoid impacting the test time and reliability of the test cell.
Effortless Test Time Reduction Through DPU-16 and APU-12 Synchronisation
On the ETS364 / ETS88 family of testers, the APU-12 max sampling rate is 100 Kilo samples per second (Ksps) and the DPU-16 digital pattern sampling rate is 132 Mega samples per second (Msps). If a particular test method needs to use the digital sampling rate, then that rate will be limited to 100Ksps and it can cause longer digital pattern run time. It is not a good test method for production, so reducing test time and getting the same results will be important!
In this paper, the author will share another test method to reduce digital pattern run time and have the same APU-12 digitizer result (compare with old test method).
This paper will share the results, a comparison between the old and new method, and how much test time can be reduced.
IGData As A Way to Audit Your Test
Efficient code analysis plays a critical role in software development, ensuring code quality, identifying potential issues, and promoting adherence to coding standards. However, the manual process of analyzing and reviewing code can be time-consuming, error-prone, and resource-intensive. In this study, we propose the development of an automated code analysis report taking advantage of the IG-Data/IG-Review Plug-in customized report creation.
By incorporating the customizable report feature into the existing IG-Report tool, development teams can optimize their code analysis process and obtain insights that align with their unique project requirements. The ability to generate tailored reports will contribute to more efficient bug detection, improved code quality, and enhanced collaboration among team members. Ultimately, this feature will empower development teams to achieve higher software quality standards and deliver more robust and reliable applications.
The custom report will leverage the power of DevOps and automation, streamlining the reporting process, enhancing collaboration, and enabling faster decision-making.
UltraFLEXplus Enabling Massively Parallel Testing at Probe
The semiconductor wafer test market has been limited by signal delivery and/or parallelism of physical device layout constraints with the active area of the probe array. UltraFLEXplus breaks through these barriers with a new PTL architecture called Universal PTL. Keeping the existing architecture delivering proven system rigidity and opening the center region for applications space from existing architectures offers a new market opportunity for high parallelism testing starting with the automotive sector and potentially reaching more segments.
The new DIB frame and center stiffener provides a wider center region to over 300mm and makes it possible to strategically contact and simultaneously test devices across a 300mm wafer. This approach will reduce the total number of contacts or touchdowns to completely test the entire wafer. The proven interface of UltraFLEXplus already provides the significant system rigidity needed for massively parallel probe arrays. Opening the center region allows for a strategic placement of these testable probe sites that distributes the load over the 300mm wafer. In conjunction with routing signals to each of the DUTs, the UltraFLEXplus system architecture optimally manages these higher forces.
Teradyne's competition already has products in this market space and has reached saturation according to Customers and Probecard Suppliers. The Competitor is limited to lower site counts due to probe force limitation with their architecture and maximum signal delivery. Teradyne is targeting a market entry solution that will deliver a 63% increase in the parallel site count, a 43% decrease in touchdowns with the Q12 tester while maintaining existing force loads as delivered today on the UltraFLEXplus platform architecture.
An Inline QA Solution for ETS-800 Multisite Distributed Projects
In the semiconductor industry, the reduction of the devices test time has always been an urgent need to be able to optimize the productivity and reduce the cost of the test. On the other hand, it's critical to maintain a high level of quality on production by dedicating a part of testing to Quality Assurance check.
Perform the QA check in a dedicated test step, repositioning the devices after the Final Test, however, goes in contrast with the throughput optimization needs.
The inline QA test is performed on the device immediately following the FT test, but under the QA limits and without moving the device. So this technique is increasingly requested by customers who want to guarantee the high quality levels required, together with a reduction in the cost of the test.
Eagle Vision MST and the Productivity Tools for ETS-800 provide all the flexibility that allows us to have an Inline QA solution that can be easily integrated into test programs. In this paper is described this solution for ETS800 Multisite Distributed (MSD) projects, compatible even in single sector condition. It provides all necessary functions and integration instructions within a test program. The QA test will be enabled on the fly, according to a predetermined execution frequency set by the user, performing the quality tests following the FT flow, on a certain device or on more at the same time. To control the QA test execution, the solution will take advantage of the potentials of the new TerMSTApp CsharedDataArray Class to manage communication between the sectors.
Locations & Details
United States
- Austin, TX – Mar 26, 2024
- Irvine, CA – Feb 28, 2024
- North Reading, MA – Mar 14, 2024
- Plano/Dallas, TX – Mar 28, 2024
- San Diego, CA – Feb 29, 2024
- San Jose, CA – Feb 26, 2024
Europe
- Binyamina, Israel – Feb 28, 2024
- Catania, Italy – Mar 19, 2024
- Munich, Germany – Mar 7, 2024
- Rousset, France – Mar 12, 2024
Asia
- China
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- Beijing – Mar 12, 2024
- Shanghai – Mar 7, 2024
- Shenzhen – Mar 14, 2024
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- Hsinchu, Taiwan – Mar 21, 2024
- Malaysia
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- Kuala Lumpur – Mar 5, 2024
- Penang – Mar 7, 2024
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- Seoul, Korea – Mar 21, 2024
- Singapore – Mar 1, 2024
- Yokohama, Japan – Feb 27, 2024
TUGx Resources
Through TUGx, we strive to deliver local access to our technical personnel, sharing knowledge and making you an expert, as you gain a deeper understanding of our products and services. The content presented at the seminars is intended to help you get the most out of your Teradyne test equipment.
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Gallery of Past Events
