Siemens Streaming Scan Network Overview
Original Author: Dwayne Dohmann
Dwayne Dohmann joined Teradyne in 1999 and has served in a variety of applications focused roles, including complex SOC applications manager. He has over 25 years of test and applications experience and is currently responsible for supporting the UltraFLEX family with a primary focus on digital solutions. Dwayne holds a BS degree in electrical engineering from Texas A&M University..
Siemens has introduced a new technology Tessent™ Streaming Scan Network (SSN) for delivering scan data to IP blocks. Streaming Scan Network also known as SSN is an EDA IP that includes methodology for generating ATPG and diagnosis. Once integrated in devices, SSN will reduce scan test data volume and allow efficient testing of multiple cores in parallel. It enables the designer to lower risk and development, in regards to ATPG scan testing. SSN is a bus distribution network along with local IP block that generates DFT signals that streamlines data distribution in the design. SSN support two basic modes – “tester-compare” and “on-chip compare”. Within each of these modes there are options to support “throttling” and “rotation” of scan data to fully maximize the bandwidth of the scan data bus and minimize pattern execution time. Each of these use cases have potential new requirements in the ATE. This presentation gives the user a starting point to understanding SSN and key differences in use cases.
Siemens Streaming Scan Network Tester Compare Operation Overview
Original Author: Dwayne Dohmann
Dwayne Dohmann joined Teradyne in 1999 and has served in a variety of applications focused roles, including complex SOC applications manager. He has over 25 years of test and applications experience and is currently responsible for supporting the UltraFLEX family with a primary focus on digital solutions. Dwayne holds a BS degree in electrical engineering from Texas A&M University..
Co-Author: Christopher Cassidy
Chris Cassidy is a Factory Applications Engineer for the US CSOC Digital & Tools group at Teradyne, where he is responsible for ongoing support with design-ins and new IG-XL features. Prior to graduating with a BSEE from Wentworth Institute of Technology in 2020, Chris completed internships across a variety of focus areas at companies such as iRobot and Analog Devices.
Siemens has introduced Tessent™ Streaming Scan Network (SSN) IP that can be included in devices to help with reducing scan test data volume and to allow efficient testing of multiple cores in parallel. SSN support two basic modes – “tester-compare” and “on-chip compare”. This paper will review the basics of the SSN Tester Compare operation and then review recent updates made to IG-XL on the UltraFlexPlus to assist the user with implementing efficient test instances for devices utilizing SSN Tester Compare. Topics covered will include how to encapsulate data mapping information extracted from the EDA simulation output into binary pattern files, review new data objects to efficiently identify failing cores after an SSN pattern burst, and review new language to allow the user to easily apply core masking without modification of the SSN pattern files.
Siemens Streaming Scan Network On-Chip Compare Overview
Original Author: Christopher Cassidy
Chris Cassidy is a Factory Applications Engineer for the US CSOC Digital & Tools group at Teradyne, where he is responsible for ongoing support with design-ins and new IG-XL features. Prior to graduating with a BSEE from Wentworth Institute of Technology in 2020, Chris completed internships across a variety of focus areas at companies such as iRobot and Analog Devices.
Siemens has introduced Tessent™ Streaming Scan Network (SSN) IP that can be included in devices to help with reducing scan test data volume and to allow efficient testing of multiple cores in parallel. SSN support two basic modes – “tester-compare” and “on-chip compare”. On-Chip Compare allows for reduced scan test time with the parallel testing of any number of identical cores. This paper will begin with an overview of On-Chip Compare, explaining its functionality, and how it interacts with SSN's other operating mode, Tester-Compare, and the impact this has on the SSN bus when failures are mapped to cores. Next, challenges that come with using On-Chip Compare will be covered, starting with the ATE conversion process. Information embedded in the STIL or WGL that describes how the device has implemented SSN must be extracted to ensure the test is performed properly. When the test is being performed, this information is used identify failing device cores, and alter the test setup with JTAG to ensure that, when necessary, all required diagnostic information is collected in a manner compatible with Siemens’ diagnostic tools.
Productivity Tools: Complementing Core Software to Deliver Enhanced Development Efficiency
Original Author: Julia DiChiaro
Julia DiChiaro is the SEG marketing manager responsible for Productivity Tools at Teradyne, where she is responsible for bringing tools and technologies developed by field and factory apps engineers to the user community to improve development efficiency, time-to-market, and the overall user experience. Prior to this role, Julia was a field applications engineer and ASIC test engineer. She holds a Bachelor of Science in electrical biomedical engineering from the University of Vermont.
Co-Author: Massimo Zambusi
Massimo Zambusi is a Factory Applications Engineer at Teradyne, where he is responsible for Productivity Tools and Field support on Flex and ETS-800 platforms. Prior to this role, Massimo was the Automotive Expert Community Leader and Field Applications Engineer. He holds a degree in Electronics Engineering from Politecnico di Milano - Italy.
The Productivity Tools suite in eKnowledge has grown from a small collection of apps-developed useful utilities to an essential toolkit in achieving faster debug and time-to-market. While Teradyne’s core software delivers tester-focused improvements in every release, Productivity Tools complement our core software by focusing on enhancing the user experience and efficiency. By combining customer needs and requests with a rapid development and release process, tools that are created by local teams to address gaps or customer requirements can now be picked up and further developed, productized, and supported to allow delivery to the wider customer base.
As a result, apps engineers now gain access to an ever-expanding toolset to make their jobs easier and achieve impressive results. This presentation will cover the latest collection of Productivity Tools on the ETS-800 and IG-XL based platforms, the results apps engineers have seen, and how to quickly get up and running using the tools.
Tuning UVS64 Bandwidth Setting To Improve Performance
Original Author: John Zhang
John Zhang is the field application engineer for semiconductor test division at Teradyne, where he is responsible for providing and implementing the test solution for the J750, UltraFLEX or UltraFLEXplus tester. Prior to Teradyne, John has more than 10 years experience in developing test solutions for RF and Mobile test. He holds a Bachelor of Electronic Information and Automation Engineering from Shanghai Jiao Tong University.
Co-Author: Shawn Chen & Troy Zhang
Shawn Chen is the filed application team leader for China solution engineer group, where he is responsible for China local customer test solution providing and project delivery on UltraFLEXplus tester and other SOC platform. Prior to application work, Shawn was in hardware team for device interface solution, and he has been in Teradyne for 11 years. He holds a Master of engineering management from Shanghai Jiao Tong University.
Troy Zhang is the factory application engineer for digital and software tools group at Teradyne, where he is responsible for high-speed digital test solution development and supporting Asia Design-Ins. Prior to this role, Troy was the field application engineer at SEG China. He holds a Master of Science degree in Precision Instrument Engineering from Shanghai Jiao-Tong University.
Now more and more projects pay attention to their digital ability and performance. To improve the yield rate on the extreme condition, the SHMOO and VMIN performance are considered, especially the Power which has big current. With the low Voltage and big Current, the Power will has large Droop and Kick during dynamic load, which may cause Pattern test fail. UVS64 has good Droop and Kick performance to match the requirements, but it can’t reach its best performance if BW is not set correctly. The BW value must be set according to the DIB bypass capacitance and ESR value, then the Power can be close to its best dynamic performance. The paper will introduce how to manage a good PI performance on DIB design, and calculate the BW value based on the DIB bypass capacitance and ESR value on programming, and after that how to tune the BW value by analyze current and voltage profile to get the best performance. With all the effort, SHMOO and VMIN can be improved.
Generating ASCII Scan Fail Logs on UltraFLEXplus – ScanFalcon
Original Author: Trevor Karrett
Trevor Karrett is a Factory Apps Engineer based out of the North Reading office. His work is focused on optical test of microLED displays for AR and VR devices, and prior to that he worked on SW tools for big digital devices.
The UltraFLEXplus scan fail data logging performance has been optimized for producing data in STDF format using the STDF V4-2007.1 scan extension in a high throughput production environment. The major EDA vendors can directly extract the required information for their diagnostic tools from STDF. However, when doing Engineering debug there may be times where the preferred workflow and output format is an ASCII-based fail log file directly written from IG-XL. ScanFalcon is an IG-XL Custom Data Consumer which can utilize the same data packets used to create the STDF output file and transform that packet content into an ASCII fail log. It supports creating output in formats compatible with major EDA vendor tools or allows the user to customize the ASCII content via custom format definition files. While there is a slight throughput impact, ScanFalcon can take full advantage of the optimized hardware fail data transfer and the bulk of the processing is done outside the main IG-XL process. This paper will describe ScanFalcon, how to use it in IG-XL programs, provide an overview of its customization capabilities.
PortBridge Expedites Complicated SOC Debug by Integrating Comprehensive Industry Tools
Original Author: Richard Fanning
Richard Fanning is the software architect for the PortBridge project at Teradyne, where he is responsible for developing the software, marketing the product and determining the product roadmap. Prior to working on PortBridge, he worked on numerous products for the FLEX, UltraFLEX and UltraFLEXPlus platforms. He holds a degree in Computer Science from Harvey Mudd College.
Co-Author: Conner Clark
Conner is a software engineer for the digital software group at Teradyne, where he is responsible for the development of Teradyne’s PortBridge software. Prior to Teradyne, Conner was a systems engineer at Aerojet Rocketdyne. He holds a Bachelor of Science in computer engineering from University of California, Irvine.
Testing SOC CPUs, like ARM based processors, on Automatic Test Equipment (ATE) presents unique challenges to engineers as device functionality cannot be confirmed through DFT alone. Production tests require an additional measure to evaluate functionality, typically accomplished by having a firmware engineer develop an ATE specific image. Since developing this firmware is predictably debug intensive, resolving issues on the ATE without tooling support can be a cumbersome undertaking. PortBridge provides the capability to run a high-level debug tools like ARM Development Studio or OpenOCD directly on the DUT using the ATE, reducing debug time and simplifying the bring-up process. Integration with these programs allows firmware engineers the ability to develop directly on the ATE on an industry-standard toolset and eliminates the need for time consuming simulation or emulation. Additionally, to allow collaboration across geographically distributed teams, PortBridge provides the ability to remotely connect to and debug the DUT.
How PortBridge’s Amplified Test File Feature Maximizes Analog Functionality Debugging
Original Author: Richard Fanning
Richard Fanning is the software architect for the PortBridge project at Teradyne, where he is responsible for developing the software, marketing the product and determining the product roadmap. Prior to working on PortBridge, he worked on numerous products for the FLEX, UltraFLEX and UltraFLEXPlus platforms. He holds a degree in Computer Science from Harvey Mudd College.
Co-Author: Conner Clark
Conner is a software engineer for the digital software group at Teradyne, where he is responsible for the development of Teradyne’s PortBridge software. Prior to Teradyne, Conner was a systems engineer at Aerojet Rocketdyne. He holds a Bachelor of Science in computer engineering from University of California, Irvine.
Embedding analog functionality into standard protocol testing has always been a challenge. Our PortBridge solution provides easy to use, out-of-the-box support for standard protocols, including test program APIs, remote access, and automatic design file integration. It also provides a mechanism for parsing files that the Design and DFT engineers already generate as part of their workflow. These files can be loaded, executed, and debugged on the ATE with no conversion needed. Incorporating analog instrument control in line with standard protocol operations allows files to be used directly from the design environment with sequences of protocol transactions and analog operations. The PortBridge toolset gives the user the ability to debug specific problems easily. At production time, everything can be optimized for maximum performance. This opens the door for a new method of testing that maintains design time concepts of abstraction and removes time-consuming translations into ATE specific formats.
PortBridge Integrates On-Die Sensor Technology into the Test Environment Seamlessly
Original Author: Richard Fanning
Richard Fanning is the software architect for the PortBridge project at Teradyne, where he is responsible for developing the software, marketing the product and determining the product roadmap. Prior to working on PortBridge, he worked on numerous products for the FLEX, UltraFLEX and UltraFLEXPlus platforms. He holds a degree in Computer Science from Harvey Mudd College.
On-Die sensors are revolutionizing system health and performance monitoring in the field as well as during ATE test. Device complexity is increasing, test program complexity is increasing and time from silicon arrival to product ramp is decreasing. Test engineers need solutions they can integrate quickly into their existing test flows that allow them to reduce debug time while improving test coverage. proteanTecs provides cloud based, technology agnostic data processing on their wide range of supported die sensors. This includes real-time decision models and uploading captured results to the cloud for cross-insertion learning. PortBridge integrates proteanTecs solutions seamlessly into IG-XL, providing a clean optimized, multi-site interface. This talk will cover customer successes in this area and new features added to further enable customer data collection and analysis.
The DSP Difference Between UltraFLEX+ IPQ8 and IP750
Original Author: Triston Ma
Triston Ma is a factory applications engineer for image sensor at Teradyne, where he is responsible for application development of image sensor testing. Prior to this role, Triston was responsible for application development of high speed digital testing. He holds a master degree in Testing & Measurement Engineering from Shanghai Jiaotong University.
Co-Author: Shuichi Ueno
Shuichi Ueno is the factory application engineer for image sensor devices at Teradyne, where he is responsible for technical support for the IP750 and UltraFLEXplus testers. Prior to this role, Shuichi was the logic designer in engineering department. He holds a Master of Engineering in electronic engineering from Kumamoto University.
UltraFLEX+ IPQ8 is Teradyne’s new generation UltraFlexPlus-based image sensor ATE test platform. Derived from UltraFLEX+ Q12, UltraFLEX+ IPQ8 has a lens tube space for 150mmx150mm internal halogen illuminator unit for image sensor test and towerless prober docking for optimal signal paths. In terms of instruments, UltraSrial20G-DP, a new image capture instrument is designed for IPQ8, it can capture image sensor outputs based on the DisplayPort protocol up to 9.9Gbps.
Same as IP750, the existing Teradyne image sensor test platform, UltraFLEX+ IPQ8 also has IDP (Image data processing) subsystem which is the image data processing infrastructure that is built on top of the UltraFLEX+ DSP subsystem.
UltraFLEX+ IPQ8 IDP subsystem enables superior performance by improved backgrounding capability and more optimized integration of software and hardware, it is being developed to offer better technical capabilities then IP750.
This document introduces the difference of DSP concept between UltraFLEX+ IPQ8 and IP750, how to convert the IDP program from IP750 to UltraFLEX+ IPQ8 and the test time result comparison of them.
Using Limit Set to Achieve Diverse Binning Requirements
Original Author: Mars Hsieh
Mars Hsieh is the Field Application Engineer for test program development at Teradyne, where he is responsible for test program development for the UltraFLEXplus tester. Prior to Teradyne, Mars was the tester engineer at Novatek. He holds a Master of Science in Electronic Engineering from Huafan University.
Co-Author: Vinson Peng
Vinson Peng is the application engineer for field customer support at Teradyne, where he is responsible for working with the customer to develop the test program for UltraFlex and UltraFLEXplus. He holds a master degree in Electronics and Computer Science from University of Southampton.
In order to meet various test requirements, the number of test items for larger SoC device is increasing day by day. To analyze the results of test items, it is needed different binning methods to find the test results of the test items in efficiency for specific test items. There are many methodologies to accomplish binning in tested result, and using limit set is a one of faster and flexible method in IG-XL. Limit set can carry out multiple binning requirements application, such as normal usage of binning which stops the testing immediately when the test item is failure. The other binning methods, the binning result of the test will be judged after a numbers of test items to expected bin. In another word, the test result is sorted by specific group instances or block with the failed items. In addition, it is also able to manage suppress binning application for developing, debugging and production requirements. Limit set is an existing feature in IG-XL to support and maintain the diverse binning function for test engineers and production engineers prosperously.
Concurrent Test Capabilities on the UltraFLEXplus
Original Author: Leo Di Bello
Leo Di Bello is the Factory Applications Engineer at Teradyne, where he is responsible for defining requirements for next generation instruments on J750 and UltraFlex family testers for testing Microcontrollers and Smartcards. Prior to this role, Leo was a Field Applications Engineer based in Munich supporting European customers on J750 and J971 systems.He holds a degree in electrical communications engineering from University in Ulm, Germany.
Using concurrent testing as a method to reduce test costs has been on the radar for more than a decade now. Concurrent testing can have advantages in many different applications. Some may think about doing analog or parametric tests while the internal MBIST is occupied with a longer Flash tests, testing different modules with different LBIST tests at the same time or simply testing 2 ports simultaneously. Any of these methods can reduce touchdown times or test program runs significantly.
However, in many cases so far, limitations of the device’s or the tester’s capabilities have prevented the introduction of concurrent testing. Now, the architecture and instrument features of the UltraFLEXplus like the asynchronous pattern starts and the increased ratio of patgens per instrument can make concurrent testing easier.
This presentation describes the work done to demonstrate concurrent test capabilities on the UltraFLEXplus. It will show different use cases and how they are being implemented on the UltraFLEXplus. It will also describe differences from the existing UltraFLEX instruments and the advantages of the new PACE architecture for concurrent testing.
ADAS Device with Best ATE Solution – Based on UltraFLEXplus
Original Author: Liangyu Qu
Liangyu Qu is the field application engineer at Teradyne, responsible for kinds of system on device chip support, such as transceiver, image sensor, large scale digital chips. Prior to Teradyne, Liangyu was a RF engineer at Spreadtrum.
Co-Author: Yu Yang
Yu Yang is the field application engineer for digital chip at Teradyne, where she is responsible for the development of ATE test solutions on the UltraFLEXplus and J750 tester. She holds a Bachelor of Engineering in Automation from Xi 'an Technological University.
As the development of autonomous vehicles, ADAS will be probably next economic growth point, especially for semiconductor market. Compared with consumer semiconductors, ADAS products have larger size and higher power consumption, thousands of pins and hundreds of current requirements; most of these feature's lead to ATE test challenges, such as load board application area, power droop/kick, high speed signal loopback. Except for above, high site count is growing forward to decrease cost.
UltraFLEXplus is the most powerful SOC test platform of Teradyne, bring a lot of priority for LSIC test. We will introduce the tester advantage of ADAS product, such as more DIB application area, flexible FRC, protocol aware, frequency counter etc. Also, we will share some general technical test experience for this device type. such as MIPI, PCIE, DDR, UFS, USB and so on. At the same time, some project design experience such as handler, DIB design experience will be mentioned.
Best Practices for Converting a J750 Test Program to the UltraFLEXplus
Original Author: Daniel Murphy
Daniel Murphy is a senior factory applications engineer for the semiconductor test division at Teradyne, where he has been responsible for providing applications support for Teradyne engineering, marketing, and field applications for over 20 years. Dan has a bachelor's degree in computer engineering from Lehigh University and a master's in computer science from the Polytechnic Institute of NY, now part of NYU.
Co-Author: Bob Brodner & Xefrem Bergman
Xefrem Bergman is a field application engineer at Teradyne's Plano office, where he is responsible for working with customers on the UltraFLEXplus tester. His most recent work was a conversion project from the J750 to the UltraFLEXplus, working on a power management device. He holds a Bachelor of Science in electronic systems engineering technology from Texas A&M University.
How easy is it to move from the original IG-XL platform, the J750, to the newest IG-XL platform, the UltraFLEXplus, and why would anyone want to do that? To make a conversion to UltraFLEXplus worthwhile, one must achieve lower cost of test through higher site counts and faster throughput by taking advantage of features of the UltraFLEXplus PACE Architecture. Furthermore, conversion needs to be as automated as possible using available tools.
This paper will discuss a successful J750Ex to UltraFLEXplus conversion for a power management device. We provide an overview of the conversion goals, the differences between the platforms that needed to be addressed, the available tools that facilitated conversion, and the challenges faced during the conversion process. On the hardware side, we discuss how instrument alignment to requirements affected DIB design considerations. On the test program side, we discuss workbook, pattern, and VBT conversion strategies. Lastly, we discuss how the project was able to meet its COT and correlation goals, providing a guideline for future, similar conversions.
IP750 New Image Capture Instrument for MIPI CSI-2 C-PHY/D-PHY Combo
Original Author: Kuniaki Ishida
Kuniaki Ishida is a factory application engineer for Image Sensor Device at Teradyne, where he is responsible for evaluating new image capture instrument for IP750 tester. Prior to this role, Kuniaki was a test development engineer at Operation group.
In recent years, smartphones and other mobile devices has equipped with higher resolution CMOS image sensors that requires higher data rates.
MIPI CSI2 D-PHY and C-PHY specifies physical layer defined by the MIPI Alliance for image data exchange between image sensor and AP and widely adopted by many mobile devices. The MIPI D-PHY is a general differential transmission line consisting of two pins per lane. The MIPI C-PHY is a complex differential transmission line with three pins per lane. Since there is no clock line, it has the advantage of saving pin counts.
In addition to the MIPI D-PHY, which has been the mainstream interface for image transfer, more and more image sensor devices support C-PHY as well. We had released the image capture option, ICUL, ICUL1G and ICMD for high data rate. ICUL supports for capturing SMIA CCP2 data. ICUL1G supports for capturing the SMIA CCP2, MIPI CSI-2 D-PHY and custom serial output data up to 1Gbps. ICMD supports for capturing the MIPI CSI-2 D-PHY and custom serial output data up to 1.5Gbps.
Now, we introduce the new IP750 series instrument, ICMCD, which can measure image sensors that support C-PHY/D-PHY combo.
UltraFLEXplus Enhanced Features for Analyzing and Datalogging Pattern Bursts at the Pattern Set Element Level
Original Author: Stephanie Kirk
Stephanie Kirk is a field applications engineer in the solutions engineering group at Teradyne, where she is responsible for developing test solutions and supporting customers on IG-XL test platforms. Prior to Teradyne, Stephanie was a test engineer at Texas Instruments. She holds a Bachelor of Science in electrical engineering from the University of South Florida and a Master of Science in electrical and computer engineering from the University of Arizona.
Co-Author: Tak Ip
Tak Ip is the senior software engineer for digital and serial instruments at Teradyne, where he is responsible for design and development of instrument software in UltraFLEX/UltraFLEXplus testers. He holds a Master of Science in electrical engineering from University of Southern California.
As digital devices continue to increase in complexity, the number of patterns to be executed in a test program increases accordingly. Pattern sets provide a structure for users to execute a large number of patterns consecutively. These pattern sets may be atomic, consisting of individual patterns, or hierarchical, consisting of one or more atomic pattern sets. Executing large groups of patterns as a hierarchical pattern set offers benefits to overall test time. However, this introduces challenges in datalogging information and processing results for individual pattern set elements, specifically the atomic pattern sets which make up a hierarchical pattern set. Previous workarounds to circumvent these challenges have introduced overhead to the test program and in response, IG-XL has introduced new features to provide these capabilities with low overhead.
A new statement, TheHdw.Patterns.ExecuteSet, has been added to execute hierarchical pattern sets and return an array of IPatternSetResult objects. TheExec.Flow.FunctionalTestLimit (FTL) has also been enhanced to support logging Scan Test Record (STR). With the new statement and FTL, the user can datalog STR/FTR for each hierarchical pattern set element and within an element, the user can log FTR at the per-element or per-module level. The new language also allows the user to assign unique fail bins to individual elements and set the failing cycle capture limit per element. To further support these features, IG-XL has added new capabilities to the debug display tools including the Pattern Tool, Waveform Display, and Characterization Studio, which provide additional access for the user to debug individual elements of hierarchical pattern sets. By taking advantage of these new IG-XL features, users will receive the benefit of shorter test time while maintaining binning and datalogging granularity along with the ease of debugging individual tests.
Teradyne UltraEdge2000: A Platform for Edge Adaptive Test
Original Author: Anand Bahirwani
Anand Bahirwani is a senior software architect for IG-XL software at Teradyne, where he is responsible for the software roadmap for IG-XL. Prior to this role he was a software architect for the results processing software on UltraFLEX and UltraFLEXplus as well as a software engineer on various platform components on Flex and UltraFLEX. He holds a Bachelors of Science degree in Computer Science from University of Rochester
Co-Author: Lawrence Luce
Lawrence (Larry) Luce is a Factory Applications Engineer at Teradyne, where he is responsible for RF, Microwave, DSP, PyGXL, and AI in Test, as well as the new UltraEdge product. Prior to Teradyne, Larry was the RF Test Engineering Team Lead at Freescale Corporation. He studied Microwave Engineering at the University of Arizona.
Semiconductor manufacturers continuously seek to improve yield and reduce test time with adaptive test techniques. Most adaptive test today involves a long feedback loop with test results moved outside of the test cell and actions fed back at a later time, possibly several lots later. These situations will continue to exist in cases where either human supervision is necessary or analysis is done with data from several test cells. However, with advancements in machine learning and analytics, many companies are starting to develop adaptive test algorithms and techniques that could be used with data on a single test cell from within a lot and possibly even during a touchdown. There are legitimate concerns to deploy these on host controllers due to possibility of using compute resources and impacting IG-XL throughput. Hence the need for an edge compute device.
The UltraEDGE was designed to provide a flexible and secure environment to run analytics within a tests cell. This paper will demonstrate how a user can integrate the UltraEDGE for adaptive test within the test flow as well as across the touchdowns.
Using PyGXL with Prediction Algorithms to Determine to Vmin Working Voltage
Original Author: Flora Shui
Flora Shui is the factory applications engineer in Teradyne Shanghai. She has worked at Teradyne for 11 years, where she is mainly responsible for SOC test solutions development.
Co-Author: Lily Zhai
Lily Zhai is the factory applications engineer at Teradyne, where she is responsible for developing test solutions for SOC. After graduation, she joined in Teradyne. She holds a Master of telecommunication from The University of New South Wales.
Devices need to do Vmin test to find its minimum working voltage. For IP tests, we usually use the search method to find the Vmin points. It will take lots of test time. In order to reduce test time, designers implement machine learning in the test program. We collect PD(Process Detector) and Vmin data of thousands of devices first. Machine learning could find the relationship between these data, then give the predicted Vmin value of tested devices. We only need to test pass/fail under the predicted voltage, thus test time will be greatly reduced. The machine learning model is provided by the product designer in Python code. What the test engineer need to do is send the required PD data to python function, then get the predicted voltage, do the corresponding IP test. This paper will introduce how to implement this method in the test program. We use PyGXL to send data between the VBT program and the python program.
- How to do Vmin tests with prediction method
- Test flow introduction
- PyGXL usage in this case
- Trouble shooting
Best Utilization of Vector Memory Architecture on UltraPin2200
Original Author: Javier Campos
Javier Campos is a Field Applications Engineer at Teradyne, where he is responsible for develop, debug and deployment of test solutions for semiconductor devices. He holds a degree in Electronics Engineering from Costa Rica Institute of Technology.
Co-Author: Vivian Wang, Mai Le & Bill Davis
Vivian Wang is the Application Engineer for Semiconductor division at Teradyne, where she is responsible for field support in Irvine CA. She holds a Master degree in Engineering from Stanford University.
Mai Le is a Test Development Engineer at Broadcom where she's responsible for test program development for CSG devices. Prior to this role, she was an apps engineer at Teradyne for the first part of her career. After that, she was a test engineer at Marvell and Apple with the main focus on test development on the UltraFLEX. She holds a Bachelor of Science in EE at California State University, Northridge.
Bill Davis is a strategic field product specialist at Teradyne focused on the digital and complex SOC market space using the UltraFLEX family of testers. He spent 15 years as a field applications engineer before transitioning to technical sales roles for the past 10 years. He holds a bachelor’s and master’s degree in electrical engineering from the Ohio State University.
The semiconductor industry is facing a continuous increasing complexity in the integrated circuit design which has led to more challenges in testing. One of the major challenges is the increase in parallel and scan patterns size due to new manufacturing processes and device testing requirements. The improved capabilities and performance for UltraFLEXplus digital instruments UltraPin2200 and UltraPin2200+ addresses these challenges by providing larger and pooled vector memory shared across channels, larger scan capabilities, and more flexible memory allocation to increase pattern depth. With careful consideration in channel selection the vector memory capabilities can be further utilized beyond the spec and will demonstrate how the memory is consumed by scan and functional patterns. The objective of this paper is to explore the ways to maximize the vector memory utilization with the UltraPin2200 vector memory architecture and decipher the LicenseRequirements file and allow a user to calculate/predict the appropriate memory license for the application. The techniques discussed include channel assignment considerations during pre-design DIB stage, implementation of site copy feature, and functional vector compression which have been proven to improve memory consumption in several projects with large patterns.
Plan for a Successful Network Device Conversion from UltraFLEX to UltraFLEXplus
Original Author: Daniel Lozano
Daniel Lozano is a Field Applications Engineer with Teradyne, where he is responsible for implementing and sharing new platform test techniques, diagnosing and resolving customer issues, and providing formal customer training. He holds a degree in Electrical Engineering from the University of California, Irvine.
Co-Author: Vivian Wang, John Shu & Tom Vance
Vivian Wang is the Application Engineer for Semiconductor division at Teradyne, where she is responsible for field support in Irvine CA. She holds a Master degree in Engineering from Stanford University.
John Shu is the Principle Test Engineer at Broadcom. Prior to Broadcom, John was the Field Application Engineer at Teradyne. He holds a degree in Electrical and Computer Engineering from University of California, Santa Barbara.
Tom Vance is currently a field applications engineer with Teradyne in Austin, TX. At Teradyne, Tom works with UltraFLEX and UltraFLEXplus testers supporting platform transitions, shared code libraries and creating solutions to the challenges of the day.
The UltraFLEXplus has been developed to provide many platform and instrumentation advancements. Leveraging these advancements for network switch devices, such as higher power supply density and digital vector memory enhancements, allows for increasing site count and therefore throughput. Successfully navigating the transition from UltraFLEX to UltraFLEXplus including increasing site count, requires thoughtful planning and knowledge of best practices which this paper aims to address. The information shared in this paper is based on a successful project conversion from UltraFLEX single site to UltraFLEXplus dual sites for a networking device. This will include a set of requirements to begin the conversion, suggested steps to follow for the conversion, typical challenges experienced and how to work through them or avoid them, as well as tips during hardware debug. The requirements consist of exactly what information you’ll need to have ready to start the process. Suggested steps will cover power supply selection and channel assignment, test program conversion, pattern conversion, and debug challenges.
Improving Memory Test Performance Using FLS
Original Author: Sung-Hyuk Choi
In traditional memory function test, failure data generated during pattern execution is stored in a specific space for failure analysis, and after the pattern is finished, it is analyzed through scanning processing. And to store the faildata generated during pattern execution, a physical space with a logical address proportional to the storage space of the device being tested is required. So, pattern execution time and faildata analysis time are required as time elements of the general test process, and a large amount of faildata storage space is required as space element. If the faildata can be checked and analyzed immediately while the pattern is running, we can finish analyzing the faildata of the pattern as soon as the pattern is finished. And real-time faildata can be checked and analyzed during pattern execution, so there is no need for a specific space with a logical address space. This paper explains FLS (Fail List Streaming) a new feature of the MAGNUM platform that can check and analyze fail data generated during pattern execution. Also, explanations of components used in FLS, FLS configuration, benefits, and how to use them will be covered.