Abstracts

Synopsys Streaming Fabric support on UltraFlex Family: Synopsys is a major Electronic Design Automation (EDA) company. Synopsys developed a new Technology called Streaming Fabric (SF) that integrates specific Design-For-Test blocks (DFT) for Scan compression and parallel test efficiency. Those emerging technologies imply a new approach as well as new responsibilities from the Automatic Test Equipment (ATE) perspective. Teradyne test systems are an important cog in the Workflow from Design to Test and back to Design. This presentation will describe the Streaming Fabric technologies from a design point of view with emphasis on the benefits for our customers. We will cover the change of workflow when converting patterns with Third-Party tools as well as the integration of those patterns in the test program. Teradyne IGXL Software embeds specific application programming interfaces (APIs) to support SF insertion while focusing on ease-of-use for the teams. Finally, we will present the means Teradyne is offering to collect and report results, this includes STDF and ScanFalcon.

In the partnership between design and test, it can often be difficult to exchange the specifics required for test execution because the environments are so different. This communication gets further complicated by the stil generation and pattern conversion process as vector positions can stray further from the source. Pattern tags is a new feature introduced in IG-XL 10.50 which allow for specific vectors to be annotated and these annotations can then be retrieved programmatically during validation and runtime. This presentation will describe this new feature and review the new API's that retrieve and interact with pattern tags. It will also review validation and execution performance data and discuss some common use cases for pattern tags.

Scan testing has gotten faster since customers have added SSN (Streaming Scan Network) to the design. In the past, scan testing was usually at 100MHz, but it has evolved to the highest speed of 400MHz now. Relatively, the overall timing error that can be accommodated becomes smaller. In the past, the timing was usually set fixed in the program. However, the manufacturing processes, voltage conditions, etc. may make device have some difference and then test failures and loss yield, so the timing setting becomes very important. In the past, characterization was used for timing adjustment, but characterization is relatively time-consuming in search, because the pattern requires repeated bursts, and the application result is also complex. For the problem of timing alignment in high-speed digital testing, UFplus provides new functions AutoStrobe and Edge Offset which can quickly calibrate and apply timing during the test process. It would be a more efficient solution than traditional characterization. Therefore, in this paper, we will demonstrate the benefits of this technology through an actual MediaTek project.

NFC devices are quasi pure digital devices, supplied by UVS256-HP resources driven by UP2200 digital channels, where the embedded PPMUs can do most of the analog tests. The need for low Cost of Test pushes to high site count solutions (256 sites or more). One of the challenges is measuring the capacitor inside the antenna inputs. The target site count and COT prevent from using any AC instrument, but the small capacitor value (<100pF) and required accuracy (<1pF) makes this nontrivial. Given the device input structure, a quasi-static method is applicable by using a constant current charge method while the PE’s comparators can evaluate the rising/falling time of the capacitance’s charge. The forementioned technique was implemented on a real device with 68pF typical capacitance: a correlation against old AC method has shown differences within 1pF and production test time below 100ms while the old method test time was about 1s. This paper explains how this technique can be implemented successfully on the UltraFLEXplus and how to avoid the pitfalls that would affect measurement’s accuracy.

The recent trend in the industry has been a shift towards the construction of systems by integrating multiple chiplets into a single package. This paper explores the application of the Tessent Streaming Scan Network (SSN), a revolutionary approach to scan testing, in the context of Multi-Die Chiplet Packaging. SSN facilitates concurrent testing of cores using a reduced number of scan pins, thereby decreasing both test time and scan data volume. The study focuses on a case where the customer has begun to implement SSN on the CPU die of their new device, while retaining traditional scan testing for the DDR and PCIE dies. This scenario presents several challenges, including channel assignment for multiple time domains (where different Dies run concurrently for the scan test), scan vector memory calculation, and balancing scan bit allocation across instruments. The hardware design also requires careful consideration, particularly when the SSN is operating at higher speeds (300MHz). Factors such as trace length, trace width, and 50-ohm termination need to be managed effectively. The paper will further demonstrate the potential for optimizing vector memory through functional vector compression (flexible scan pins). Finally, it will discuss the process for printing out the SSN sticky bit status in the event of failure occurrences. This paper aims to provide valuable insights into the practical application and optimization of SSN in the context of Multi-Die Chiplet Packaging.

The 3nm process for newer semiconductors offers numerous advantages, including denser transistor, performance improvements and enhanced power efficiency. However, packing more transistors in the same area increases complexity and carriages new challenges for testing. The number of cores grows while the pin counts available remain constant. Traditional scan method may result in inefficient test time and vector memory utilization. The Tessent Streaming Scan Network (SSN) introduced by Siemens aims to overcome these testing challenges by reducing the scan test data and enabling parallelism of multiple cores. The UltraFlexplus tester supports SSN in two modes: On Chip Compare and Tester Compare. Additionally, the improved capabilities and performance of the UltraFLEXplus digital instrument UltraPin2200 provide larger and pooled vector memory shared across channels, larger scan capabilities, and more flexible digital channels allocation. The objective of this paper is to explore the advantages of implementing the SSN mode On Chip Compare versus the traditional scan testing. These benefits might include test time reduction, vector memory utilization optimization, and more rapid test program development.

This paper will present and describe the newest member of the UltraPHY high speed interface test solution family and demonstrate its use not just for the highest speed SERDES interfaces but also how it could be applied to many other multi-level and encoded signaling busses. It is a fully integrated testhead instrument applying a DAC based super high speed arbitrary waveform generator as a pattern and signal generator. It is paired with a super high bandwidth ADC based digitizer to capture and analyze almost any kind of data signal. Examples of SERDES, PAMx, MIPI camera C-PHY, MIPI automotive A-PHY, DP-QPSK coherent, and other test signals will be sourced and captured. Innovative features like a live PRBS pat gen driving a DAC, super low jitter performance, and system coherent clocking will be discussed and described.

Collecting Scan fails, what's next? Introduction to Diagnosis: During the life of a device, there is a constant need for Yield monitoring. Design for Manufacturing (DFM) duty is to identify how device design can be improved to maximize production efficiency. Fault Diagnosis and Failure analysis are key elements to the understanding of the mechanisms. Scan testing, as a structural test, is a major source of information to map failures to the design. Scan data collection is mandatory to perform this analysis. It is Automatic Test Equipment (ATE) duty to collect that data at whatever level, from Engineering to Mass Production. This paper will describe how Teradyne collects and reports scan fail information. We will cover STDF scan-specific entries as well as ASCII outputs with ScanFalcon. We will then discuss the next steps and how Design teams process the results reported by the ATE to pinpoint areas of improvement in their design.

This presentation will explain how users can utilize the Teradyne UltraFLEXplus scan option for functional patterns compression. Using this methodology allows users to optimize usage of the UltraFLEXplus vector memory. We will share also some actual results of compression achieved using this methodology with an actual customer case for a very large device.

Today’s ATC systems typically rely on sensing DUT’s temperature to close the control loop. However, to react on a temperature change it usually takes a long time for the ATC system to pull the temperature back to the preset value. In this presentation the author will describe a new architecture of DUT ATC system, and with the features available on UltraFLEXplus ’s DCVS instruments, user can calculate the heat power of the DUT in real time and be able to control a Near-DUT-Heater to generate more or less heat based off the electrical power going into the DUT. By doing this, system can maintain the total heat generated by both DUT and extra heater at a constant rate, consequently the temperature shall not fluctuate as much as before without the extra design. As a result, the 3rd party closed-loop ATC system shall be able to maintain DUT temperature much easier and much more accurate.

Failure analysis is necessary in order to understand what caused the failure and how it can be prevented in the future. Electrical Failure analysis is the process of determining how or why a semiconductor device has failed, often performed as a series of steps known as EFA techniques. In this presentation, the author will introduce the ATE involved EFA techniques including LVx(Laser Voltage Probing and Imaging) and DLS/LADA(Dynamic Laser Stimulation / Laser Activated Device Alteration). After that, the author will explain the requirements for ATE to carry out those techniques, and challenges if the scan patterns being used are SSN(Streaming Scan Network) patterns. He will then demonstrate a proposal from Siemens for workflow changes to address those challenges, and a Teradyne’s tool solution for processing SSN patterns that will be used in those processes.

A pervasive challenge faced while developing and debugging test programs is the lack of integrated support for register maps. While most devices have one or many defined register maps, traditional approaches often require test engineers to hardcode values or generate custom libraries to interact with their registers by name. These methods, while functional, can be cumbersome, error-prone and do not offer a complete solution. PortBridge has addressed these challenges by enabling test engineers to load both industry-standard and custom register maps formats directly into a test program. With this awareness of the registers, PortBridge empowers users to seamlessly reference register names directly from test files and provides type-ahead capability in all IGXL test program development environments. Additionally, this feature offers an intuitive Graphical User Interface (GUI) to provide real-time visualization of registers and their corresponding fields, as well as the ability to update them dynamically as tests are conducted. These improvements radically improve the ability to bring up and debug test programs by abstracting register knowledge in such a way that engineers can shift their focus away from the hassle of managing and maintaining custom register map libraries and focus on test development and debug at a higher level.

This presentation outlines the strategies employed in the development and testing of AP class chips using the Teradyne UltraFLEXplus (UFP) platform. Our project leverages advanced technologies to integrate Chip Probing (CP) and Final Test (FT) processes, achieving improved efficiency and quality. We begin by examining the technical advancements that enable high site count testing on the UFP platform. This section introduces how to use the new PACE architecture of the UltraFLEXplus platform to address the challenges in Load Board design for high site count. It also ensures the parallel test efficiency (PTE) of each site. Additionally, we discuss increasing CP flow test coverage, including strategies for ensuring site consistency in CP binning and shifting more tests from FT to CP such as Memory-BIST etc. The implementation of the MIPI switch in the current project is also highlighted. The second section focuses on improvements in quality and efficiency through the development of a robust library of IPs common codes, characterization, and Efuse CBB. We also discuss the integration of IG link, Git, and DevOps practices, alongside custom tools like STDF analysis tool, Shmoo result analysis tool, and testing program information extraction tool. Finally, we analyze the cost implications, covering common Test-Time-Reduction (TTR) strategies for System on Chip (SoC) products, the financial benefits of high site count testing, and the cost-effectiveness of increasing CP flow test coverage.

Concurrent test is a method which is significant to reduce test time. UltraFLEXplus supports most of the concurrent test features found on the UltraFLEX. Additionally, UltraPin2200 improves patgen and PA engine granularity. DC instruments can individually be assigned to different time domains on UltraFLEXplus. These advantages make concurrent test easier on UltraFLEXplus platform. Modern devices designed with numerous independent blocks on the same die or in the same package are perfectly compatible with concurrent test features. This practice is an AIOT device which contains PMIC, analog, RF, USB, PLL blocks. Meanwhile, AIOT device is extremely sensitive to the cost. Depend on this, this paper will discuss preconditions for applying concurrent test to a project on UltraFLEXplus, basic mechanism of concurrent test and how to apply concurrent test to a project, concurrent test benefits on test time reduction based on our practical verification project. We have tested the performance of concurrent test by assembling four different block combinations in this practical project which covers the concurrency between pattern, protocol aware and DC instrument. This paper will also illustrate the efficiency, HW design requirement and potential concurrent test advice for device designers based on our best practice.

Recently LTE RF device has more than 3000 test items. It takes long time to complete the test program. after reviewing the test plan from IC designer. When the development period is pulled in than expected, the test engineer is under pressure to complete the code fast and accurately. Customized RF standard library helps the time saving for the test program development, test time reduction and easy to code and debugging. The idea is that customized standard library is matched to the format of the test plan from IC designer. It makes the information of test plan move to the test program easily and fast. And all of VBT code and the format of the test condition is reusable for next product because only small change such as specification and number of ports will be made. IGXL is based on Excel and IGXL version in UltraFlex can provide maximum 60 variables in Test Instance It makes that the necessary test information from the test plan is included to the test program. In customized standard library, the format of the test information is matched to the test plan through the cooperation of IC designer and the test items are categorized in ports(RX/TX) and block(2G/4G/5G). And in order to optimize the test program, customized standard library includes the embedded auto script to generate RF and baseband signal of UltraWave8G and UltrPac300 when validating IGXL. Her is the customer's feedback regarding the customized standard library. 1. Time saving for Test Program Development: > 50% 2. Test Time Reduction: 8.8%

UltraFLEXplus system implements the Parallel Advanced Command Execution (PACE) architecture, which enhances test execution by delegating hardware commands to embedded processors and maintaining a pipeline for strict and predictable command execution. Pattern Oriented Programming (POP) burst in UltraFLEXplus system offers significant benefits in terms of test stability and optimization of test times, Test throughput increasing and test development time reducing and Flexibility and scalability enhancing. Compared to tests based on Visual Basic for Test (VBT) , test time reduction result brought by using single POP pattern is very limited. But when POP patterns are grouped together (burst mode) the test time optimized efficient will rise dramatically even to 40 to 60%. This paper will using really test cases with RF instruments ultrawave8G,ultrawave24G as well as UPAC300 to demonstrate the benefits POP-bursting brings to customer. Pure VBT testing, POP single pattern test and POP burst testing are compared.

UltraPAC500 is new generation IQ signal instrument in UltraFLEXPlus tester. One UltraPAC500 instrument have 16 diff source/16 diff capture (8 IQ pairs), I/Q channel have 250 MHz BW to provide 500 MHz IQ BW. It have higher channel density and higher bandwidth compared to UltraPAC300 and UltraPAC80 in UltraFLEX tester. The Ultra Precision Analog Channel have native IQ capabilities for IQ waveform AWG generator and IQ waveform capture. The user model for UPAC500 is different from UPAC300 and UPAC80. The I and Q channels will be programmed as a IQ pair. In this paper, we will introduce this new generation of IQ signal instrument – UPAC500 and key best practices and loopback performance experiments result.

An RFFE module is a pre-assembled component that integrates various circuits crucial for transmitting and receiving radio frequency (RF) signals in mobile devices such as smartphones, smartwatches and tablets. It essentially acts as the bridge between the antenna and the transceiver chip, handling signal amplification, filtering, switching and other critical functions. The integration of multiple components into a single module contributes to a smaller footprint, enabling slimmer and more compact mobile device designs. As a result, ATE test solutions need to provide high-throughput and comprehensive testing of these modules with accuracy, efficiency and reduced test time. Testing RFFE modules is a multifaceted process involving functional verification, RF performance evaluation, and adherence to industry standards. Some critical parameters are transmit power level, receive sensitivity, power consumption, filter response, return loss, harmonics suppression, and linearity. This paper will outline the performance requirements and the complete Teradyne solutions to meet these challenges today and into the future. The platform offers excellence in both hardware, user friendly software and ease of customization.

Modern electrified vehicles have very dense battery packs. These packs are comprised of dozens of lithium-ion cells stacked together in a vehicle chassis. These high-density battery packs are relying on sophisticated monitoring and communication interfaces in order to detect faults and to have the cells work efficiently together, effectively increasing the battery life. There are two Battery Management techniques in use: wired and wireless. A typical Battery management scheme has each battery cell, or small group of cells, connected to high accuracy monitors. In the wired Battery Management scenario, the cell monitors are wired to each other and connected to a Central Processing Unit (CPU). The CPU takes the incoming information from the cell monitors and incorporates the data in to a track battery performance and battery health.Wireless Battery Management uses a wireless protocol like Low Energy Bluetooth to replace the wired interconnects. The potential high volume applications for Wireless Battery Management devices requires a low cost high throughput device test solution. This paper will describe Ultra-Flex instruments need to test these devices.

From tracking your lost cat to securely unlocking your car door hands-free to tracking the robots on a warehouse floor, UWB (ultra-wideband) applications are expanding. How are you testing them? On your bench setup and in characterization, you may be using the LitePoint IQgig-UWB+ test system. On your production test floor, you are using the UltraFLEXplus to test a variety of projects. What if you could combine the production worthy environment of the UltraFLEXplus with the feature rich IQgig-UWB+? The UltraWaveLX-UWB+ integrates the power of the LitePoint IQgig-UWB+ with the UltraFLEXplus, all in a clean formfactor co-located with the support cabinet. This 32-port solution is integrated into IG-XL using the logical instrument model. It is programmed and debugged within the IG-XL ecosystem like any other RF instruments and is pin-to-pin compatible with the UltraWave8G and UltraWave24G. In this paper, the UltraWaveLX-UWB+ will be introduced, the use model shared, and performance data presented.

The PACE architecture introduced by UltraFLEX plus is widely known among engineers. This architecture introduces asynchronous instructions between the host PC and DMC, resulting in the pipeline stall or pipeline full speed (also known as pipeline backpressure) phenomena. Both of these phenomena exhibit analogous behavior in timelines data, characterized by large gaps in host. A significant challenge arises from the tendency of general users to confuse pipeline full speed with pipeline stall, often leading to wasted efforts in addressing perceived but non-existent pipeline stalls. This paper presents a method to help users better understand and differentiate between pipeline stall and full speed. Additionally, a quick method for distinguishing the large gaps caused by these two phenomena is introduced.

Radar devices in the 60GHz V-band and 80GHz e-band are incorporating Antenna structures right on the Die. This Antenna-in Package technique is common practice and requires creative over-the Air test techniques. Simple V-band and E-band radar devices have a low antenna count. Usually two antennas: dedicated RX and TX antennas or one vertically and one horizontally polarized antenna. New Generation radar devices, however, are increasing antenna count upwards to 4 RX/4 TX arrays. This requires mm-wave muxing by the ATE MM-wave instrument to handle the increase antenna counts and increase site counts of these next generation radar devices. Low cost, high-density test solutions will be required to test these next generation radar devices in high volume production. This paper will explore low cost, high density near DUT radar test solutions that on the UltraFLEXplus. The near DUT radar solutions incorporate the use of the UPAC500 and DSI SPI bus and User Power Supplies as some instruments used for test with the near DUT modules.

Have you ever been sitting at your desk wishing that you did not have to go out to a tester and hook up a spectrum analyzer to understand some unexpected behavior? Even worse, get on a plane or find someone remotely to connect it for you. What if the tester could measure a spectrum up to the bandwidth of the RF instrument in use? In this paper, a method for producing a plot showing the spectrum of a DUT output using and UltraWave8G or UltraWave24G will be presented. The receivers on these UltraFLEXplus instruments can support bandwidths of up to 400 MHz; however, by taking multiple captures with different LO frequencies and stitching them together, the user can create a composite wide band spectrum up to the bandwidth of the instrument in use. Should the user decide to use this method in test time critical environment, the UltraFLEXplus PACE architecture and DSP backgrounding can be implemented to optimize test time while still making wideband measurements. In this paper, the authors will present the theory behind this method, walk through some example code and its implementation, and give an example use case that can be easily adopted to your needs.

mmWave frequency range, not only coax cable, but also RF trace on board characteristics is affected to measurement performance and accuracy. Typical DUT circuit in RF, one side is with RF connector, another side is open-ended. Simple way of RF path loss in DIB is, measuring double length of RF trace and calculation of Bisect, simple scalar math is no issue, however if calculation on vector level, having magnitude error at closing 0 or +/-Pi range in phase. RF instruments of UltraFLEX and UltraFLEX plus have OSL (Open-Short-Load) is as standard calibration. However, OSL calibration is difficult to measure RF trace on DIB, especially, one side open-ended line. When measuring this kind of RF trace line on DIB, customized OSL calibration standard kit is required for each device and package type. TRL (Thru-Reflect-Load) calibration does not require precision calibration standard as like OSL calibration. TRL calibration is consist of some different length RF trace line and a reflect (open or short) line is made in DIB. This calibration standard is able to be made by DIB at same time. In same DIB or separately as coupon board. This paper will cover topics which are about fundamentals, what is advantage, evaluation result and also challenging parts will be explained as well as issues that arose during design and testing.

Wireless Radio Frequency (RF) transmitters typically have a Power Amplifier (PA) connecting the signal chain to an antenna for transmission. Depending upon operating conditions, the PA can introduce non-linear distortions to the signal which results in impairments in the overall transmission integrity (e.g., ACLR and EVM degradation). Generally, there is a trade-off between PA operating in the linear region at the expense of power efficiency vs PA operation with higher power efficiency at the expense of linearity. With a PA operating close to the 1dB compression point, distorted signal measurements and calculations can be made which result in a way to modify the desired signal input to the PA. The net resultant PA output signal is closer to the desired linear output signal by use of Digital Pre-Distortion (DPD). The UltraWave8G provides a mechanism for implementing DPD utilizing Look-Up Tables (LUTs). This DPD method operates on the digital source samples provided to the UltraWaveModulatedSource resulting in a pre-distorted source input to the DUT PA. Subsequent testing can verify linearity at the improved power efficiency operating point due to DPD at the DUT PA output. This paper will explain the use of DPD with the UltraWave8G and provide results from a working example.

Automotive Imaging Radar devices are a new upcoming market, targeting applications to detect and analyze object movements around the car. It brings promising new technology to automakers worldwide that enables more intelligent vehicles. These devices are part of a comprehensive driverless system that enables autonomous mobility. As a key part of sensing systems for automated driving, imaging radar will be an enabling element for automated driving features on highways and urban environments. Those devices are mmWave transceiver devices, operating in the 76 – 81 GHz frequency range. An innovative test solution has been developed, to allow the test of those devices at mmWave frequencies on the UltraFlexPlus test platform. The test solution, called DX81, consists of several compact modules placed in the DIB board application space. It allows bidirectional, transmit and receive DUT testing in the 76-81 GHz mmWave frequency range. It is a highly integrated, IGXL supported, suited for multisite high volume production test.

E-band automotive radar is an important growth area in the millimeter wave testing industry. Teradyne currently offers UltraFLEXplus RF solutions up to 24GHz. In this paper, a DIB based modular expansion solution for automotive radar testing on the UltraFLEXplus is introduced. On the UltraFLEXplus tester, an UltraWave24G instrument is used in conjunction with either an up-converter module (UCM) or a down-converter module (DCM) to source or measure a 76 to 81 GHz continuous wave (CW) signal. An optional switch Front-End-Module, either a single-throw-six-pole (SP6T) FEM or single-throw-eight-pole (SP8T) FEM, can be combined with either the UCM or DCM to present six or eight waveguide ports to the DUT. When using a DIB extension instrument such as these frequency converters, calibration is a concern. This paper will further describe the calibration solution and its usage in the production setting. In this paper, the authors will introduce the DX81 DIB extension instrument, review some key specifications, and present the calibration method.

Ultrawave8G synthesizer per channel has multiple benefits in RF testing, There are 2 methods of sourcing multi-tone signal using ultrawave8G, 2 channel combining mode and Single source  MultiTone(SSMT) which is the new introduced for RF instruments in UltraFLEXplus. IG-XL generates single source multitone using the modulated source when you use the normal multitone VBT programming model, however for the 2 channel combine mode, it uses an internal combiner to combine 2 adjacent channels in same module. Through simple mode enable and disable, SSMT and 2-channel share same IGXL coding.  Compare to 2 channel mode SSMT has higher test parallel efficiency with comparable high performance. Teradyne Result Viewer (TRV) is a Data Application Server (DAS) that receives data events from the Test Event Messaging for Semiconductors (TEMS) protocol. TRV tool has ability to perform immediate statistical analysis in an interactive engineering environment; more efficient method to view/filter results compared to using ASCII files; TRV tool also has ability to focus on particular sites, tests or types of tests from the total data collection online and offline. It provides a graphical display of health and stability of full test program or particular test. This paper will use TRV tool to  analyze UW8G 2 multi-tone mode with  above programming

A follow up to the 2024 paper introducing UltraPort-PCIe and UltraPort-USB, this paper will provide a deeper dive into performing Scan over high-speed IO ports such as PCIe and USB. Beginning with an overview of the technologies involved, the paper will discuss the solutions available from Synopsys and Siemens to enable scan over high-speed IO ports on a device. Next the new cross-platform FlexTest tools will be introduced, including the Serial Scan Tool, supporting new file formats for the technology. Support on the UltraFLEXplus with UltraPort will then be presented. This will dive into the instrument specifications supporting USB and PCIe scan, including pattern memory and scan fail processing that are unique to this approach to scan testing. Software features will also be shown, including workflow changes and datalogging functionality. Finally, proof of functionality will be given as a result of partnering with Siemens and Synopsys using FPGA DUT proxies.

ICMCD (Image Capture MIPI C-PHY D-PHY) is a new image capture instrument for the CIS tester(IP750ex and ip750exhd). Conventional ICMD could capture MIPI D-PHY up to 1.5G bps, but by using ICMCD, D-PHY can be captured up to 4.5G bps, C-PHY can be captured up to 3.5G sps, and simultaneous capture of C-PHY and D-PHY combo devices is also possible. In addition, the maximum capture angle has been changed to 1G pixels. By using these functions, the diversity of supported devices has further evolved. In this presentation, I will introduce the specifications of ICMCD, the difference in hardware features depending on the docking method, software-related features, and comparison with conventional instruments. Finally, I will briefly explain how to program it. We hope that this instrument can provide you with a better solution in the future to enable testing of new products and reduce the time and cost required for testing.

MIPI D-PHY is a flexible, low-cost, High-Speed serial interface solution for communication interconnection between components inside a mobile device(1). MIPI capturing on ATE systems is historically done using MIPI receiver circuitry (or "BOST" solution) on a device interface board (DIB). While such a solution can parse the data and provide the payload directly, the data captured by these receivers is usually sent to the tester using much lower-speed interfaces such as SPI or I2C, meaning increased overall test times as compared to a direct capture. Moreover, Digital Signal Processing (DSP) is still required to extract the desired info from the payload. By leveraging the Digital Capture (DigCap) function in UltraPin2200’s Digital Signal Source/Capture (DSSC), in conjunction with its Source Synchronous functionality, it is possible to capture MIPI D-PHY payload data directly up to 2.2Gbps per lane. DSP can then be used to extract the payload data and perform any required operation to extract the desired info in one go, providing a faster, more efficient test, with reduced DIB cost and complexity. In this presentation, I will explain the requirements, including DIB signaling, and provide a step-by-step guide on how to implement a MIPI D-PHY direct capture solution on the UltraFLEXplus. (1) MIPI Alliance, Inc., “Specification for D-PHY SM”, ver. 3.5, 29 March 2023.

Integration circuit (IC) fabrication is very complicated, as many manufacturing steps have to be executed on the same wafer. All fabrication steps are subject to errors, wafer defect patterns are the results of various problems in the fabrication and wafer test process. Thus, the wafer map defect patterns can be used to identify sources of errors in the manufacturing process. Recently, local defect pattern recognition has attracted a lot of research interests. The results of wafer test are usually presented in a wafer map, which gives locations of failed dies in a wafer. There is plenty information of Machine learning and wafer map recognition patterns on published research, the idea of this paper and project is to use this information as leverage to create a pattern recognition system for Teradyne testers, that will detect patterns automatically when running production on the clients' sites. This will give added value to our services and will help our clients to recognize manufacturing issues quickly.

ETS-364 is a top runner platform at many customers for decades. ETS-800 is the high site count evolution, which offers a tremendous boost in throughput and Cost Of Test. Despite the two platforms having similar instrumentation, the multisite solution on ETS-800 is seldom a copy of the ETS-364 test concept, as the native ETS-800 resources and APEx are the key enablers. Porting applications to ETS-800 requires converting the Visual Studio project from VS2005 to a modern version, the EV project into EV-MST, the project structure into ETS-800 syntax. This also requires the user to map legacy resources to new ones (like UPD-64); APEx and DIB HW connections need to be considered when updating the code. The user will want to convert the analog resource patterns (AWG) into the new resource syntax. The digital vector EVD has to be converted into eDST WKBK, and all the timings and levels context have to be properly translated and merged into eDST profiles. The Teradyne Convert2ETS800 Productivity Tool makes all this easy and fast! Convert2ETS800 = Ease of Use + Time To Market.

Before IG-XL 10.40, VBA is more of a scripting tool in IG-XL for test program development. As the test codes are growing larger, those Legacy Codes are hard to maintain or may become unreadable. It may take hard work to add a brand-new test code or refactor the whole test program. C# is now the new supporting language in IG-XL test program development after IGXL 10.40.10. Compared with VBA, C# is a powerful and versatile object-oriented programming language that has become an essential tool for software development on .NET platform, so we can use the features (inheritance, overriding, overloading…etc.) of OO programming in IG-XL test program development to let test codes more readable and structured. Design Pattern is another tool that is used to solve the problems of Object Generation and Integration when moving to object-oriented programming. In this paper, we will introduce some Design patterns that can be used in IG-XL test program development. Singleton Pattern could solve the object generation problem and reduce unnecessary memory usage. Adapted Pattern simplified the structure of each Test Method in IG-XL. The Factory Pattern the complex test items or large data to be more organized. The implementation of Design Pattern might let IG-XL program develop more efficiently and developing.

With the rapid development of artificial intelligence technology, AI chips have become the core hardware driving progress in this field. However, accurately assessing the performance of AI chips and implementing efficient grading is a key issue faced by current ATE testing. This article aims to introduce an AI chip testing solution based on the UltraFLEXplus (UFP) platform, discussing its application in functional implementation, Partial Good grading strategy, and thermal management. Firstly, the article will briefly introduce the universal testing solutions for CPU/GPU/AI chips implemented on the UFP testing platform, including traditional Process-Voltage-Temperature (PVT) analysis, Physical Layer testing (PHY), Scan testing (SCAN), and Memory Repair (MR). Subsequently, considering the grading requirements of AI chips that necessitate a comprehensive consideration of computing speed, memory bandwidth, power consumption, application scenarios, scalability, and other specific functions, this article will focus on introducing a multi-site, systematic testing and grading method based on UFP. A demo program will illustrate the process of Partial Good grading to readers. Lastly, in view of the high current issues that AI chips may encounter during testing, the final part of this article will explore the design of thermal management and current monitoring schemes. This includes over-temperature protection mechanisms, simultaneous profiling functions for voltage & current, and the design of current monitoring circuits for core power supplies. In summary, the AI chip testing solution based on UFP proposed in this article enhances testing efficiency and accuracy. The discussions on thermal management and current monitoring provide strong support to ensure reliability and stability during the ATE process.

At the core of Teradyne’s Analytic Management Platform (AMP) is the UltraEdge2000 server, capable of executing Machine Learning models during device test. When moving any software solution from development to production deployment, real world possibilities must be considered. This paper will discuss lessons learned and best practices to be followed when developing and deploying machine learning models on UltraEdge2000 from an IG-XL test program. Topics to be covered include – Deployment methods - Docker or XAR, which is best and when? Communication methods – Sockets or FIFOs? Adapting to testers that do not have UltraEdge hardware or libraries Best practices for server applications developers.

This presentation shares use cases of Teradyne DevOps in actual project development, highlighting the use of DevOps to automate manual tasks and enhance the quality and efficiency of the project development process. This project utilizes Teradyne's self-developed DevOps process (DevOpsForTest), which integrates IG-Review, IG-Data, and IG-Correlate to offer solutions to customers. First, the rules of IG-Review are customized based on the customer's inspection specifications, and each rule is graded to assist test engineers in quickly identifying and resolving issues. Furthermore, the TestInsight tool is used to batch convert patterns and merge timings, while IG-Data automatically generates DFT test items. This eliminates the need for complex manual operations, significantly reducing human errors and improving development efficiency. Lastly, IG-Correlate is executed automatically through DevOps to generate customized reports and collect execution results for integrated analysis. This enables test engineers to gain deeper insights into the test results across test runs, instruments, and even platforms. It also provides a solution for achieving site-to-site correlation and lot-to-lot correlation.

At the core of Teradyne’s Analytic Management Platform (AMP) is the UltraEdge2000 server, capable of executing Machine Learning models during device test. A key component to this solution is a transparent multisite use model that matches IG-XL to make it seamlessly integrated into IG-XL. This paper will discuss the multisite implementation of the UltraEdge instrument and best practices to be followed when developing and deploying machine learning models on UltraEdge2000 from an IG-XL test program.

In recent years, the complexity of devices being tested has increased significantly. This complexity has become a challenge for developers. Engineers now need more time to develop tests than before. The key to solving this challenge is to optimize the development process and improve efficiency. In my presentation, I will propose a solution that utilizes software tools such as OASIS, MyInfo Copilot, and TRV. These tools provide a way to efficiently proceed with development tasks. By adopting them, customers can shorten time to market and reduce the burden on engineers. For example, MyInfo Copilot is easy to use because engineers can ask questions in their local language, saving time reading extensive help files. In addition, the Oasis tool IG-Link allows engineers to manage programs more modularly. This also allows debugging by multiple people, and by linking with the version control tool (Git), engineers can easily control versions. In addition, Oasis has a wide range of support tools. In addition, IG-XL currently supports programs in .NET. By utilizing third-party tools such as GitHub Copilot in the development environment Visual Studio, engineers can not only improve the quality of their code and save time, but also get new ideas from GitHub Copilot. TRV is a tool that allows users to observe program behavior in real time, eliminating the need to analyze STDF files and allowing users to analyze debug data on the fly. In conclusion, the Teradyne software presented here provides solutions that can reduce engineers' workload. We hope that this presentation will interest customers in these valuable tools and encourage them to adopt them.

Abstract for Defect wafer map detection: Wafer testing is an important step in judging the quality of chips on wafers and plays a crucial role in yield assessment. After wafer testing, the judge information for each chip on one wafer will form a wafer map where 0 denotes out of wafer, 1 denotes PASS and 2 denotes FAIL. The defect patterns on wafer maps are often induced by some issues in the manufacturing process and some patterns keep recurring during the process. Defect wafer map detection aims to detect the wafers with special defect patterns for root cause analysis, which is useful for yield optimization. This work used multiple machine learning strategies. We firstly used a pre-trained model called DINOv2 to convert raw wafer images into image embeddings. Then, using those embeddings, we trained models such as Neural Networks, XGBoost, and LightGBM among which LightGBM reached the best performance. After checking the incorrect predictions, we performed label enhancement on some wrongly labeled wafer maps, leading to a 2% increase in model accuracy. Moreover, we added some symbolic features like yield rate, coordinates of failed mass center and the normalized distance between failed mass center and wafer center onto embeddings for training, which resulted in another 2% increase in model accuracy. Additionally, after looking into the Renesas data, we are working towards redefining some wafer defect patterns for specific products based on their own special defect root cause. Our defect wafer map detector may be used to help process engineers make decisions during the wafer testing process. Keywords – wafer defect map, AI for test, classification, Symbolic AI

Semiconductor manufacturers seek adaptive test strategies to optimize their test efficiency. To provide adaptive test solutions, test engineers need to link data from the test cell to custom AI/Machine Learning models that can provide a dynamic response to alter the test program execution. Using Teradyne's recently introduced Analytic Management Platform (AMP), this presentation will demonstrate how test engineers can readily create portable customizable solutions that leverage their AI model's knowledge to alter IG-XL test program execution without requiring persistent job changes. We will compare two categories of adaptive changes: changes that can be requested asynchronously, such as disabling tests, and changes that require being done synchronously immediately after a touchdown, such as a rebin operation. A walk-through of a customized rebin solution for IG-XL using the UltraEdge will be covered during the presentation. This presentation will highlight how AMP and its SDK can easily support integration with a wide range of AI and Machine Learning models, enhancing the test engineer’s capability to harness the power of their test data to make real-time decisions that can improve overall test outcomes.

With the Industrial 4.0 movement, we see more and more advanced digital technologies being produced, and more and more integration of such intelligent technologies into manufacturing and industrial processes today. In 2023, there was an opportunity to explore a project in the areas of Robotics and Automation for a customer. In collaboration with an engineering team from Universal Robots (UR), we (the Strategic Software - Production Integration Team) have prototyped a tailor-made solution for a use case envisioned by the customer. Through this work of integrating UltraFLEX IG-XL with the UR5e program, we were able to able to direct and control the UR cobot from the IG-XL system – automating the processes of picking, placing, testing, and sorting of devices. As you can imagine before, how hand test would go is have an engineer use a pop-sucker to go pick up a chip from a tray, move it to the test head of the tester, secure it in place, then move to the tester desktop to hit run to start testing. And once it is done, the engineer would have to go to the test head, disengage the lid, use the pop-sucker to pick up the chip and bring it over to an output tray. But now with this solution prototyped, everything is handled by the UltraFLEX tester and the UR. From input tray to a pre-aligner, to the test head. And once testing is done, the robot will pick up the chip from the test head and send it to the designated output tray based on bin results. The aim of this paper is to introduce the work of the integration effort and spread knowledge about it in hopes that this would serve as a springboard to other integrative applications between Teradyne products in the future and potentially create new businesses to offer customer efficiency through automation between Teradyne's products.

The advancement of Artificial Intelligence (AI) technologies demands a collaborative approach that leverages the strengths of both academia and industry. Strategic partnerships between leading technology firms and prominent academic institutions have proven essential in pushing the boundaries of AI research, adoption, and ethical implementation. Examples from industry giants such as Meta, Google, etc. highlight the substantial benefits and unique importance of these collaborations. Meta collaborates with Stanford on AI ethics, natural language processing and pioneering responsible AI technologies, while Google partners with UC Berkeley to optimize machine learning algorithms and develop scalable AI solutions. For example, Stanford's Human-Centered AI (HAI) initiative has been key in incorporating ethical design and human-centered thinking into AI development, ensuring technologies are responsibly developed and aligned with human values. These collaborations combine academic research's theoretical depth with industry's practical applications, accelerating AI innovation and ensuring real-world applicability, scalable solution, and ethical considerations. Our collaboration with Northeastern University specifically moves forward the frontiers of AI innovation in semiconductor testing areas like Device Interface Board (DIB) design optimization, explainable AI for robust testing, and AI agents for software/test engineering. Using DIB design as an example, we will develop a domain-specific compilation flow for testing resource allocation. This will analytically express the constraints of instrument and channel assignment. We will create training datasets and use reinforcement learning to optimize the resource allocation for the initial Big Analog device under test. Preliminary results and productivity improvements with the AI-driven optimization flow will be demonstrated.

Although there are a several TUG papers about the DSSC on the ETS-800 and a few that use and/or analyze parking loops, there is no Step-by-Step paper on how to make a parking loop from scratch. The result of this lack of training is that I have seen several test programs for large, 90+ pin chips which are paying upwards of several seconds of test time. In this presentation we will cover the following topics: First, we will introduce all aspects of the DSSC coding that need to be placed in the .cpp file. Then, we will introduce all aspects of the various instructions and lines in the eDST vector file. Next, we will show how to implement a DSSC parking loop for both an I2C and a SPI. Lastly, we will review the test time benefits for both protocols as compared with vec write commands. We will explain the differences between the START, STOP, CONTINUE and START_AND_STOP engines. Then we will look at how to set up a user created functions to correctly parse address, data and R/W information. Next, in the section concerning the necessary components of the eDST file, we will look specifically at how to set up the pattern and waveform sheets. Then, we will discuss how to implement the parking loop properly using the C1 and C2 cpp flags. Finally, in the last two sections, two parking loop examples (one for I2C and one for SPI) will be considered. While reviewing these examples the test time improvements of the DSSC will be highlighted. In addition to providing step-by-step instructions for creating your first parking loop, this paper will also provide optimized working code for both I2C and SPI DSSC parking loops. Many customers should be able to leverage these coding examples directly for their needs depending on the specifics of how their chips implement these protocols.

On any tester platform, most production test programs require resource sharing for the best cost-of-test. To improve test economics, a higher site count is desired, which demands more instruments in the test head, unless resource sharing is applied to better utilize the existing configuration. However, thorough resource utilization planning is mandatory to avoid making mistakes when developing the test concept block diagram. With medium to high pin count devices, this can become a tedious and time-consuming task, especially when using many sharing elements like multiplexers, matrices and relays. To keep the overview about which resource is required on which device pin at what point in time, a bulletproof method is required to identify the sharing opportunities while preventing resource conflicts. This presentation outlines a simple step-by-step process starting from test specification to an optimized solution using a table called Resource Utilization Grid (a.k.a. the RUG) to balance resource usage and instrument sharing along the test flow to achieve highest site counts on the ETS-800 utilizing its innovative APEx architecture.

Until recently, the UltraFLEX family of ATE consisted of one platform and one programming language. With the introduction of the UltraFLEXplus, measurements and measurement library code should ideally support multiple platforms. In addition, coincident with the rollout of another platform, the addition of .NET programming introduces two more programming languages, thereby creating a 2x3 matrix of use cases for ATE Test Engineers to learn and support. This matrix imposes a requirement for modular test program development. Further, when these technologies are coupled with a change to a Distributed Version Control System (Git) as well as Productivity Tools (Oasis), a new workflow is needed to support daily test development activities. This paper shares lessons learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub into a productive workflow for test program development.

While transitioning to writing IG-XL test programs in .NET, specifically in C#, the move from procedural programming to object-oriented programming is taking place. A major part of this transition is consideration of this question, “What is a Test Method?” This paper dissects the traditional monolithic test method and transforms it into a composition of smaller methods. There exists multiple drivers for this architectural transition. The first of which is to leverage object-oriented programming techniques made available in .NET and C#. Next, the need for fully vetted reuse libraries is driving more generic solutions, as well as Unit Testing. However, not every piece of the test method content should be part of the reuse library. Instead, some pieces should exist in the device-level code so that is can be customized by each team and even each Product Engineer. So, we will consider the components of a test method and access what content needs to be library code and what content needs to be carved out of the library, effectively splitting the traditional test method into smaller parts that don’t all live in the same place. This architectural shift optimizes both reuse and flexibility.

This paper introduces a convenient, code-based option for loading Arbitrary Waveform Generator (AWG) patterns using the SupportCodes MFLApp RampsLoader. Traditionally, the ATE (Automated Test Equipment) AWG Pattern Editor has been the standard tool for creating AWGs. However, when more than 10 AWGs are required for a test application, the default ATE AWG Pattern Editor becomes cumbersome, tedious, and slow, complicating the preparation process. Collaborative efforts among multiple engineers often lead to AWG file conflicts, resulting in file corruption and significant time loss due to recompilation, even for minor changes. Frequent addition and modification of AWGs are integral to the development and debugging process. This presentation will detail the use of the SupportCodes MFLApp RampsLoader, including code examples to create 16x Battery Management System (BMS) cell voltages with AWGs and actual scope captures. The potential applications for the SupportCodes MFLApp RampsLoader are vast and limited only by one’s imagination. Additionally, the implementation of SupportCodes MFLApp RampsLoader enhances workflow efficiency by providing a streamlined and automated method for AWG pattern creation and management. This not only reduces the likelihood of human error but also significantly cuts down on development time. The capability to seamlessly integrate this loader into existing testing frameworks ensures minimal disruption while maximizing productivity. By leveraging this tool, engineering teams can focus more on innovative problem-solving and less on the mechanical aspects of AWG pattern generation.

MyInfo Copilot aims to elevate how test engineers interact with key pieces of information to improve their efficiency with Teradyne products. This presentation is to provide users with a snapshot of the existing capability, recap the methodology used for providing the LLM with contextually relevant information, discuss ways that Teradyne has prioritized IP protection, review how quality is optimized, and cover the benefits for why each of these design decisions were chosen. As of today, MyInfo Copilot comprehends information about UltraFLEXplus, UltraFLEX, ETS-800, and ETS-88 Family of test platforms, it’s capable of providing users with productivity tool identification when applicable, and able to reference TUGx presentations and test techniques to provide users with feedback from user-based expertise.

As time goes on, the complexity of devices continues to increase, while engineering teams are pressured to develop test solutions as fast as possible. Teradyne developed the Remote Connectivity Matrix (RCM) to support test engineering teams meet these demands by reducing time to market. When scattered geographic locations can limit the productivity of test engineering resources, having a way to increase the amount of productive remote debugging is essential to meet the needs of an evolving global industry. The RCM enables global teams to increase their productivity, and when used in concert with other tools, can reduce the effort needed to arrive at a quality test solution. While the ETS-800 already provides four sectors’ worth of debugging potential by separating a single engineering tester into four independent debugging stations, adding the RCM and oscilloscopes (and appropriate DIB design) to this setup can aid geographically diverse teams in developing a test solution fast and reliably, by eliminating most of the need for manual probing. This paper demonstrates the implementation and benefits of using the RCM in an engineering environment in a recent test development project.

In 2024, IG-Correlate was introduced as a tool that can be used to provide insight into pre-correlation data. User feedback has driven enhancements in data readability, visibility, accessibility, and support for additional pre-correlation analysis use cases, as well as performance improvements. These updates have shifted IG-Correlate to better align with user expertise and usability expectations. Such can be seen in core features like the Readiness History Comparison, the Quick Stats panel, and the Measured Data plots, where the accessibility and representation of data has been adjusted and improved. New functionality such as Multiple Datasets and Target Sets give the user more control over the assessment of their data. Since it's introduction, IG-Correlate has continued to improve the Test Engineering pre-correlation experience by enabling users to focus on and evaluate key problem areas. Through the simplification of that assessment process, Test Engineers can more efficiently investigate, improve, and resolve unstable tests.

The Tester Abstraction Layer (TAL) is a novel approach to ATE test design that provides a platform-agnostic and extensible Application Programming Interface (API) in order to simplify test development. TAL is designed to abstract away the complexities and idiosyncrasies of individual testing platforms and provide a unified, easy-to-use API for test development. This abstraction layer allows test program developers to write tests once and run them on multiple platforms without any modifications. TAL acts as a bridge between test program logic and the underlying testing platforms, encapsulating differences between the platforms and translating generic test commands into platform-specific instructions. TAL additionally allows for test portability. Since TAL provides a platform-agnostic API, tests written for one platform can be easily ported to another platform. This can be particularly useful with multi-tiered test strategies, where common test logic needs to be executed on multiple platforms, such as ATE and SLT, to ensure test completeness. This document will describe the design principles, benefits, and applications of TAL, namely siting the Tester API project.

Design engineers generate test patterns that are typically handed off to test engineers to be incorporated into an integrated test program. As test program size, chip complexity and the number of patterns needed for complete coverage grows, the cost when these newly introduced patterns fail increases exponentially. This leads to lengthy iterations between designers and test engineers. DesignLink provides a web-portal that allows design engineers to submit patterns for testing into an automated, out of the box solution, that will compile, test and gather full execution results. This provides the test engineering team with confidence in the pattern while also tracking a full status of all the patterns for a particular device which gives team leaders a general overview of the bring up status.

In semiconductor testing, accurate and efficient logging of results is crucial. IG-XL offers integrated mechanisms to log results into Standard Test Data Format (STDF) files, ASCII datalogs, or display them in an output window for immediate verification. While these built-in options cater to many standard needs, certain applications require specialized logging solutions tailored to specific customer requirements. To address these needs, IG-XL supports the attachment of custom data consumers. This presentation will delve into the general interface provided by IG-XL for custom data consumers and introduce ScanFalcon, an existing custom data consumer uniquely designed for ScanFailProcessing. ScanFalcon enhances the flexibility of data logging by allowing users to define the output log file using a format definition file and adjust settings through a configuration file. We will explore the key features and benefits of using ScanFalcon, including its adaptability to various logging requirements and its ability to streamline the data verification process. Attendees will gain insights into the implementation and configuration of ScanFalcon, demonstrating how it can be utilized to optimize semiconductor testing workflows.

The .NET Development in IG-XL feature adds two new programming languages to a Test Engineer's arsenal: VB.NET and C#. But .NET is so much more than its languages -- .NET is an entire ecosystem. I will demonstrate how the multiple facets of the .NET ecosystem can improve a Test Engineer's efficiency, from C# inside Visual Studio, through Oasis, DevOps and your own personal toolkit developed in PowerShell or .NET.

The UPD-64 is a mixed signal instrument which has a broad feature set and its introduction greatly improved the capability of the ETS-800 Test Platform. At this point, APEX is a well-known and highly utilized capability of the UPD; and, this paper will continue to give examples of optimizing APEX usage. Furthermore, this paper continues by highlighting other significant features that exist and can be leveraged in the planning phase of a DIB Design. Knowing these features beforehand and designing them into the DIB can enable Test Engineers to obtain more significant contributions from the instrument. This includes examples of where and when to make specific design considerations and improving positive satisfaction of requirements on both ends of the mixed signal spectrum. In summary, this paper is set upon the goal of making the instrument a more significant and broad contributor to successful designs within the ETS-800 test platform.

Between 2022 and 2028, the largest revenue drivers for the Power Semiconductor market will be in EV, Automotive, Industrial Motors and Consumer Electronics. EV (20% CAGR 2022-28) is expected to continue significant growth into the next decade due to environmental and sustainability government initiatives. Morningstar forecasts that EVs will account for about 40% of all vehicles sold worldwide in 2030. One of the key innovations in power semiconductors is the use of wide bandgap (WBG) materials like silicon carbide (SiC). WBG materials have a higher efficiency, can hold off higher voltages, and operate at higher temperatures than the typical silicon (Si) devices. Therefore, an EV using SiC chips in the traction inverter can have 10% longer range (or a 10% smaller battery, therefore lower price) than an EV with Si chips. However, these SiC devices have unique challenges which ultimately lead to a much lower yield, which on a typical SiC device wafer can be as low as 70%, as compared to a typical silicon power device wafer which has a yield of over 95%. It is important to weed out known-bad devices prior to singulation so as to avoid the expensive step of packaging such failed devices. Some lessons learned from 50+ years of Si device production are applied to SiC. One such lesson is the use of wafer-level burn-in to do highly accelerated life tests (HALTs). These tests stress the power device at elevated temperatures with basic DC testing to ensure all failed devices are weeded out. This paper describes the technical reasons for doing WLBI for SiC power devices. We will discuss the significant drawbacks of SiC crystal growth as compared to Si, as well as unique device physics of the SiC MOSFET. We will discuss how WLBI is done, and why we believe that it will be necessary process qualification step for the foreseeable future. Finally, based on the potential growth of SiC market, a model of the total available market (TAM) will be presented.

Silicon Carbide power devices benefit from the advantages of wide bandgap materials and have the characteristics of high power, high efficiency, and high temperature resistance. They are widely used in various fields of new energy, including photovoltaics, energy storage, charging piles, electric vehicles etc. Compared with silicon power devices, the price of its silicon carbide equivalent is still relatively high, and the reliability also needs to be improved. The cost and yield of SIC MOSFET wafer play an important role for that. Improving the test coverage and efficiency of SIC MOSFET wafer is important and quite challenging due to the characteristics of high voltage and low leakage, to name a few. This paper will introduce the characteristics of SIC MOSFET devices, the challenges of multi-site wafer testing and demonstrate the ETS88Duo DP32 test solutions & result for SIC MOSFET.

In recent years, the market size of power discrete devices has been expanding due to the growing demand for EVs. Unclamped Inductive Switching (UIS) testing is a required test for Power MOSFETs, which are typical power discrete devices. UIS testing is required at the wafer, KGD (Known Good Die), and package stages. The UIS test turns on the DUT, stores current in the L load connected in series with the power supply on the drain side, and then turns off the DUT to make the DUT operate in avalanche by the back EMF of the L load and the power supply voltage, and measure the energy during the avalanche period. Since DUTs with low avalanche immunity are destroyed during UIS testing, the measurement circuit requires a protection circuit to prevent circuit component destruction in the event of DUT destruction. This presentation will introduce a low-cost, flexible, and fast failure prevention circuit using GreenPAK. In this method, we can reduce the number of components, time to debug circuit and module size because of using GreenPAK which allow user to easily develop logic circuit on one chip by arranging symbols and parameters on software "Go Configure" provided by Renesas.

Digital pattern control is managed, internally, through pattern sequencer (PSQ) commands. That feature set is clearly denoted and taught to new users. An extension of that command set provides the ability to control analog resources on the ETS-88/364 as well, and this is also referred to with PSQ nomenclature. New users are provided information to be aware that such features are present, but further instruction is not provided. Experienced users sometimes have an empirical subset of knowledge of this feature set, based upon specific examples targeted at specific DUT test needs. This presentation is intended to provide both new and experienced users with an awareness of the full feature set, and approaches to make use of that, for multi-site test solutions development. For analog resource control, a “programmer’s reference model” of the hardware can be provided. This model can be thought of as a switch matrix. Separate steps are undertaken to set up the signal paths, and then to drive signals on these paths. These signals then cause the analog resources to act, with clocking structures commanded from the ETS-88/364 digital pattern board. Many earlier presentations have provided references to what was done with the PSQ hardware, to achieve specific customer DUT-management goals. These reviews are excellent, for situations where another customer seeks to implement similar actions, and when a reference to that earlier presentation is available. This presentation is oriented, instead, towards describing the hardware feature set, from a customer utilization standpoint. This is done, such that both new and experienced users can be aware of what is potentially possible with the tester hardware supporting PSQ operations. The intent is for users to leverage this information and become fully productive in this area. The starting point for these explanations, is the point where the ETS-88/364 training class materials leave off, with the operations of the bidirectional transceiver test device.

Battery Management System (BMS) devices are pushing the boundary of ATE, requiring greater accuracy, higher voltage, and high site counts. The typical approach to testing requires more VI channels than can fit in a tester. DIB application hardware, like a resistor ladder, can help alleviate tester resources and increase site count. Though it has proven helpful, there are challenges with device loading, noise, and drift. Teradyne has developed an application module that addresses these challenges. The Battery Management Extension (BMX) module plays two key roles in BMS applications: 1. High precision floating low noise stacked voltage reference with extremely low thermal drift. 2. Higher density (site count), low-cost test solutions due to resources that are freed up by the BMX Module. In this presentation we will review applications that use the BMX and review best practices for its implementation. We will also review the performance of the BMX in actual applications over time and temperature.

With the development of consumer electronics, a variety of different charging protocols have emerged, and protocol chips also play an important role in this application. Even in the charging field of automotive electronics, the application of protocol chips is more and more important. On the other side, to minimize costs, some protocol chips also integrated a buck or boost in it. This paper introduces a protocol chip (This chip also integrated a buck) test solution for automotive application and developed based on ETS-88. In this solution, we will introduce how to develop 4site's protocol chip test on ETS-88. We also introduce how to design the DIB, how can we get a better test time. Below are some highlights for this solution: 1. There are some high-resolution ADC in this chip and one LSB is less than 1mV, we can test it directly in ETS88 and we can also verify it with SPU pedestal mode which accuracy is close to a 6-bit voltage meter in lab. 2.We can also get a fast test time with advanced ETS test method such as DSP tool. 3.We can get a very high PTE for 4 site testing with MST shell. 4.Design the DIB to avoid noise and interference.

The continued growth of electrification of vehicles has driven the need for communication ICs with thousands of volts of isolation. Production level partial discharge testing allows manufacturers to ensure and specify the isolation level as well as the leakage through the isolation barrier. It goes without saying that devices with high isolation and lower inherent charge (pC) have an increased value in the market. To accurately and repeatably test these devices, one needs a solution that can stress these devices to the industry specification and accurately measure the inherent charge. In this TUG paper, we will quickly cover the market and why these devices are required, with focus on electrification of vehicles. At a high level, what systems in a vehicle require this technology and why. Then we will deep dive into the specifications of partial discharge and the current industry standard and the challenges that it created for mass production testing with thousands of volts of specified and guaranteed isolation. We will also cover what values semiconductor manufacturers can benefit from with robust, accurate, and repeatable production test solutions. Finally, wrap up with the latest Teradyne solution and the benefits it can provide to the industry.

In the automotive industry, the introduction of xEV = HEV (Hybrid Electric Vehicle), PHEV (Plug in Hybrid Electric Vehicle) and BEV (Battery Electric Vehicle) is accelerating to develop vehicles with low environmental impact in line with the trend toward carbon neutrality. As this becomes more familiar to the public, xEV Inverters need to be smaller and thinner, and there is strong market pressure to reduce costs, so it is necessary to reduce the number of parts. Recent 6in1 SiC (Silicon Carbide) modules for xEV have added product value by incorporating snubber capacitors within the module. This integration requires attention to test conditions and some techniques are needed. In addition, by mounting SiC KGD (Known Good Die) in parallel inside the module, the total current capability is increased, and the number of DIB parts (especially relays) increases accordingly. Therefore, we offered AC only, DC only, and AC/DC indexed parallel in one ETS-88TH DUO to provide a more flexible solution.

Over the past few years PortBridge has evolved into a robust solution on the UltraFLEX and UltraFLEXplus platforms. This paper will cover how we expanded that feature set onto the ETS-800 platform. The technical challenges encountered included initializing and interacting with PortBridge from C++, enabling the interactive tool usage from Visual Studio breakpoints and utilizing DSSC on the platform. We will cover module recording which allows the user to parse a sequence of operations once and reuse those multiple times throughout the flow. Test file support allows design files to run directly on the platform with minimal code and the remote connect feature enables usage of EDA tools on the tester real time. The combination of PortBridge and MST provides a highly efficient and versatile solution. It enhances testing capabilities and streamlines the development and debugging processes, making it an essential tool for engineers and developers in the semiconductor industry.

Overshoot on the VCE signal during a short circuit test on an IGBT, SiC or Mosfet always manifests at the time the device is switching its state from On to Off. This overshoot represents a threat to the integrity of the device because in some cases the peak value of this signal can surpasses the breakdown voltage or even the maximum electrical specifications the device can handle, therefore damaging the device. In the case of Power Discrete applications when designing a PCB that will execute a whole flow of tests (including the Short Circuit Test), parasitic inductances are introduced to the circuit creating or increasing the overshoot the device will experience. There are several techniques that are applied in the field to reduce this effect, like changing the Rg resistor on gate, manipulating the VGE value, or adding a snubber circuit on the design, but these techniques often do not resolve the issue completely and in some cases generate other problems for the field engineers. This project proposes a dv/dt feedback control method that uses a capacitor placed in parallel to the miller capacitance of the device, introducing a current di/dt to the control circuit in order to change the dv/dt response of the device, therefore reducing or even eliminating the overshoot generate by the application itself.

This paper introduces the external switching buffer module which is a newly custom designed for HVMU 2.0 instrument direct path. Despite the instrument’s robust performance, it suffers from channel count limitations within a single slot configuration. The conventional approach of adding external relays on the PCB surface is insufficient due to issues related to isolation from relay power noise and susceptibility to electromagnetic interference (EMI) induced by high voltage switching. Also, its fixed 50ohm termination input condition could not be guaranteed by most Rogoski coil suppliers for full range peak performance. As an integrated solution, this module is designed to solve those problems at once. This module incorporates an impedance-changing buffer with external relay switching input and it offers a standalone +/-14V clean floating power source isolated from the common DIB supplies. More interestingly, this module is shielded by full metal cover for both sides, top and bottom. It is then assembled with specially matched plastic components to provide the best possible noise immunity.

With the introduction of towerless UltraFLEXplus, the test cell footprint or floor space has been largely consumed by universal manipulators to manage larger and heavier testers. Semiconductor manufacturers are requesting more test capability in smaller footprints to avoid building new test facilities. UltraFLEXplus meets these reduced footprint needs while maintaining existing towerless signal delivery, rigid architectures, docking interfaces and maintains the existing DIB frame architecture for smooth transition with existing products. Hinge manipulator features on UltraFLEXplus does not stop there. Added benefits also include a host of new improvements such as: better docking repeatability, integrated probecard security, and automated OPD docking operation for fully automated (hands-off) testing capability. This paper will introduce a new probecard orientation and prober loading for hinge test cells. Also included are details of feature enhancements which not only add value to the Customer for future test floor operations and planning, but simplify cable and hose management, less test cell setup complexity, and overall stability over time. The significant benefit of reduced footprint with the UltraFLEXplus Q24 that doubles the instrument quantity or signal capability with no impact to the test cell footprint as compared to the smallest tester in the UltraFLEXplus family. Hinge manipulators are available with all major prober suppliers with no need to change existing prober Supplier.

Partial discharge is a localized breakdown of the insulation material of an electrical device. Partial discharge testing is of high importance on optic and magnetic isolators due to its capability of forecasting early defects on such devices. The ETS-88 UHV is designed to perform these types of tests at high voltage in compliance with IEC-60747. With an electric vehicle market demanding greater withstand for isolating parts, having components tested at higher voltages is a must. However, the test bench under which the high voltage is applied could become a source of PD (Partial Discharge) noise if the design is not performed carefully. Partial discharge tends to be a non-repeatable and unexpected behavior by the sole nature of the effect itself. This means high voltages require more reliable and robust designs that isolate the effect of the DUT (Device Under Test) from the rest of the hardware. Designing a low PD noise environment can be exhausting to debug. Hardware can confound the designer as the PD can't be seen or measured directly with instrumentation on the DIB. This presentation will provide techniques such as PCB design, cable arrangement, clearance and creepage, material selection and structural support, which will be based on both theoretical and empirical knowledge.

This paper presents the technique for implementing a 'sync to ID number' function and a FOR_EACH_SECTOR macro. The sync to ID number function causes each sector to sync to exactly the same point in the code. This functionality is not currently available using the existing SyncStations() API. The FOR_EACH_SECTOR macro is similar to the FOR_EACH_SITE macro, but instead loops individually though each sector, rather than each site. The problem that needs to be solved comes from the implementation of the SyncStations(int iSyncId) command available to users as an MST API. The way this command is currently implemented, although the iSyncId ID number of the sync point is available for debug purposes, the sectors are not guaranteed to sync to the same ID point in the program. This means that when trying to sync the sectors together the user can easily end up causing the sectors to 'ping-pong' instead. As we will explain in the paper there are many times the provided APIs are more than sufficient. But there can be problems in multiple cases. This paper presents a solution to these problems using the cross-sector, shared memory resources of TerMSTapp to write user application code that is aware of the sync point that other sectors are at. It also tracks if the sector is frozen a that sync ID point, or if it is between sync points. Using this information when sectors get out of sync 'lagging' sectors are freed to catch up to 'leading' sectors and only the front most sector is paused at a sync point as all of the other lagging sectors catch up to it. A user adjustable max sync wait time is also provided and discussed. Finally, this paper discusses specific use cases where it is important to sync each sector to the exact same point of code in order to avoid the possibility of significant test escapes.

Based on productivity tools such as IG-Link, IG-Log, and IG-Review, are designed to align with the customer's test plan, generate the test program, and then return the test program to the test plan. This approach ensures that the test patterns and conditions precisely match the designer's plan and customer requirements. By integrating these tools, we can significantly reduce development time and expedite mass production, thereby enhancing both quality and efficiency. Specifically, the Test Program Generator takes test data from the RD’s test plan and the standard test library (STD) to create IGXL programs using IG-Link. Meanwhile, the Test Program Auditor utilizes data from IG-Review and IG-Logger to compare it against the designer's test plan, ensuring full alignment. These tools offer several key benefits: Compatibility: IG-Review, IG-Logger, and IG-Link, maintained by Teradyne, are compatible with J750 UltraFLEX and UltraFLEXplus platforms. Ease of Use: The tools simplify the creation of source files for IG-Link. Accuracy: They facilitate easy comparison of IG-Review reports with the RD’s test plan. Reliability: Customers can rely on these test programs for Teradyne platforms to deliver consistent and accurate results.

In today's fast-evolving technological landscape, the ability to develop and deploy test solutions is crucial. This paper explores the process of ETS800 test program development using productivity tools to expedite market entry. By leveraging automated frameworks and library code, we demonstrate how the test solution development phase can be significantly shortened without compromising on quality. This paper focuses on the implementation of these tools in a real-world test development environment, highlighting the benefits in terms of time savings, cost reduction, and overall product reliability. The findings suggest that integrating these tools into the development lifecycle can streamline the process, thus enabling engineers to achieve faster time-to-market and maintain a competitive edge.

Dynamic Part Average Testing (DPAT) is a key tool for identifying outliers in manufacturing processes, enhancing production quality. Although typically implemented at the wafer stage, it’s also applicable in Final Testing. At the wafer stage, DPAT can be executed inline, coded, or applied as a post-process before wafer cutting. In Final Testing, inline execution of DPAT is necessary due to the absence of further sorting. Despite the demand for a general solution or methodology for incorporating DPAT, Teradyne currently doesn’t provide one yet, as each customer has unique requirements. This paper explores the benefits of a comprehensive Teradyne solution for DPAT testing on the ETS-800. The proposed solution involves developing a Teradyne DPAT library, which would enable customers to conserve time, minimize effort, and enhance quality while minimizing the changes required to each test application. The primary objectives include standardizing inputs and outputs, simplifying user coding, and improving DPAT solutions’ test time. This approach allows users to have the flexibility to customize their calculations, promoting efficiency and precision in DPAT testing.

The UltraFLEXplus platform is the newest member of the UltraFLEX family, designed to support the next generation of digital devices. The expanded capabilities of the new system has prompted many to switch to the UltraFLEXplus, or use a combination of UltraFLEX and UltraFLEXplus to test their devices. The two platforms share many similarities, including the IGXL code environment. However, through firsthand experience upgrading and debugging test programs, we have found there are several key differences that program developers should be aware of when switching to the Plus. Through this presentation, we will share tips, tricks and lessons learned for transitioning programs between the two platforms, as well as additional considerations needed to take advantage of all improvements achieved by the UltraFLEXplus. This hands-on guide focuses on practical advice for anyone either starting on or moving to the new platform, and includes discussion of the latest instruments and innovative test techniques available.

The ETS-800 Test System natively supports I2C functionality to allow many I2C controlled peripheral devices to be utilized on the DIB or Family Board. This is very useful for adding support circuitry to aid in DUT testing. As site counts grow significantly and I2C communication increases, test time is impacted by the slowness of I2C coupled with the amount of communication required. This starts to eat into throughput via longer test times.SPI peripherals operate at much higher frequency or clock rates yielding significantly faster communication times compared to I2C. Historically, the ETS-800 does not natively support using SPI peripherals without utilizing HSD pins which takes resources away from testing the DUT. An underutilized resource on the ETS-800 are the PSQ signals dedicated to the DIB. There are 4 PSQ signal lines per sector to the DIB. This presentation will show how these 4 PSQ signal lines can be used to operate SPI protocol peripherals on the DIB or Family Board which will improve communication speed as well as open new opportunities to use more advanced circuitry that is not available with I2C.

Git is a powerful revision control software that enables flexible and collaborative file management for local and global teams alike. However, compiled IGXL files obscure specific revisions in Git, which blunts Git’s effectiveness in identifying, tracking and merging individual edits to sheets and code modules. Thus, ideal test program repositories keep files stored as ASCII. This makes Git perfect to pair with the IG-Link tool of the Oasis suite, which allows users to build IGXL subprograms, jobs and workbooks from a codebase of organized ASCII files. The combination of the two software tools allows for one unified codebase to span multiple platforms (such as UltraFLEX and UltraFLEXplus) as well as multiple software revisions (such as IGXL 9.10 and 10.50). Over the course of multiple projects, a Gitflow-style approach to repository maintenance has allowed a Teradyne team to maintain a golden, working copy of each device’s test program during active development and debug. In this presentation, I hope to share the most effective ways we have found to start, debug and maintain a test program between platforms and software revisions.

This presentation provides a guide to fully utilize the two main operational modes of the DSSC engine, namely the Parallel Mode and the Serial Mode. These modes are selected based on the specific requirements of the Device Under Test (DUT) and are crucial for optimizing test efficiency and performance. In Parallel Mode, each channel of the engine is read per vector step. This is suitable when there is a need to read multiple channels simultaneously. On the other hand, in Serial Mode, the DSSC reads only one bit per vector step, reducing the DSSC readback time for a DUT with a single serial output pin. Notably, due to the limitations of the DSSC engine, even for device pins with serial communication, selecting Parallel Mode can be more beneficial for multi-site usage. The presentation will discuss the characteristics, advantages, limitations, and test times of these modes. It will also discuss how to appropriately select and apply these modes to optimize test strategies.

Most low cost MCUs have embedded 10 or 12-bit ADCs. Testing those ADCs usually requires precise analog instruments to drive a ramp in sync with a pattern. Especially with higher site counts at wafer test, the need for many of those precise instruments can lead to an increased cost of test. The UltraFLEXplus UP2200 digital instrument has a PMU per pin, and the accuracy and linearity is appropriate for testing 10 and 12-bit ADCs. Having a PMU behind each pin allows testing multiple sites or ADC inputs in parallel to reduce test time. In addition, the PMU can also be used to drive ramps for threshold tests or trimming. Up to now, synchronizing the PMU with the pattern required using pattern CPU flags to repeatedly jump back and forth between the pattern and an interpose function. This use model has unnecessary complexity and overhead due to the hand shaking between the pattern and interpose function. A new PMU feature has been introduced to support pattern synchronous ramp generation, without the need for interpose functions. This simplifies test development and makes optimal use of the PACE architecture and background processing of the UltraFLEXplus. This paper will describe how to use this new feature and its capabilities on synchronizing the signal with a pattern module. It will then demonstrate a proof of the solution on a real device in production and compare it to a solution using more precise instruments.

When testing ADCs or DACs with 16-bit resolution or higher, the QMS is a good candidate and will only need some considerations to ensure good accuracy and enough resolution, especially for those devices under test (DUT) with very low non-linearity specs (less than 1 LSB) and high voltage ranges (greater than 10V). As a rule of thumb, the chosen measuring instrument should have ten times better resolution and accuracy than the devices being tested. This is where additional techniques may be required to enhance accuracy when measuring voltages with the QMS. One effective method involves implementing a pedestal voltage source along with instrumental amplifiers on the DIB and performing focused calibration with a high-accuracy digital multimeter. Together, these improve the QMS's resolution and accuracy. This paper will explain how this technique works, how to implement it, and will analyze how temperature can impact the pedestal voltage, potentially leading to incorrect voltage measurements on the DUT. The paper will also provide recommendations on how to mitigate the impact of temperature changes.

Multi-site index Parallel (MSIP) testing in Automatic Test Equipment (ATE) significantly enhances Units Per Hour (UPH) compared to conventional multi-site testing methods. MSIP allows multiple devices to be tested simultaneously across various test sites, optimizing instrument utilization and reducing idle times. Unlike traditional multi-site testing, which often suffers from sequential processing bottlenecks and inefficient parallelism, MSIP maximizes throughput by leveraging concurrent execution. This method reduces overall test time and enhances efficiency, directly translating to increased UPH. Additionally, MSIP's ability to balance workload dynamically across test sites ensures consistent performance and mitigates the impact of prolonged test time affected by scan and low current leakage testing times. Consequently, MSIP in ATE represents a superior approach for high-volume semiconductor manufacturing, delivering substantial improvements in productivity and cost efficiency.

Match loop is a very useful feature that is used in many test scenarios. Match loops allow a pattern to branch based on output from a device pin. When using Match loop, people typically pay attention to the branch condition setup. The branch condition is a crucial factor in determining whether specific actions are executed during testing. For instance, if the output of a particular device pin satisfies specific conditions, Match loop can choose different operation paths based on that condition. Different ATE platforms and digital boards will have different ways of using Match loop. By comparing the differences in the Match loop function between different platforms, we can find out the characteristics of each when applied. We will show what is match loop at first. Then this article will discuss and compare the usage methods on each ATE platform such as J750HD, UltraFLEX/UltraFLEXplus and ETS-800. This will help engineers use the Match loop function more conveniently across different platforms.

Fail log capture and analysis is necessary and very important in almost every program Functional debugging, sometimes a small batch production fail log will have to be collected, to make a tradeoff analysis. The traditional solution is to get data from HRAM or CMEM, such as SFP of Teradyne J750 and UltraFLEX; most competitors ATE platform adopt a similar way. It is less efficient and difficult to use in production, test time is a key constraint. But for the Teradyne latest SOC tester UltraFLEXplus, we have another choice. The new structure UltraFLEXplus is not only evidenced by high instrument performance and huge broadside layout area, but also the data log flow and analysis. When UltraFLEXplus writes data to STDF file, it also has an interface to copy any data (fail log included) and transfer it to user, binding with algorithm, customer can make any analysis in real time.it almost will not take additional test time. In this paper, UltraFLEXplus data consumer structure and Scan falcon simple application case will be introduced, to make the customized output as customer’s requirements, such as single test item loops and site parallel output. Scan falcon can save a lot of test time, even if it is mainly targeted for debugging. Furthermore, if customers may also want to do some basic fail log analysis for production, Archimedes will be recommended, especially the potential benefit of big digital device testing. The strengths and weaknesses comparations between Scan Falcon， Archimedes real time analysis and extract fail cycle from STDF after end lots, will also be showed to audience.

Moving to .NET, IG-XL users have now the ability to develop their test program code within Visual Studio, leveraging the power and flexibility of modern programming languages like C# and VB.NET. Besides getting more flexibility and advantages using a modern programming language, there is also a need to analyze your code, especially when it comes to executing performance. IG-XL already provides an integrated profiling tool (TimeLines), but while the driver integration makers (Automatic VBT, DSP, and Result Overhang, etc.) are still supported, there is no build in support yet to analyze non IG-XL code. This paper embarks on an exploration of various methods to overcome the existing gap in .NET source code profiling. It delves into different approaches and tools, such as the Visual Studio Performance tools, both commercial and non-commercial tools, and even manually created timestamps. The aim is to provide developers with the knowledge and resources necessary to optimize their code performance, thereby ensuring efficient and effective test programs in .NET. In addition to examining these methods, the paper also offers a glimpse into future developments and potential enhancements in this area.

When sharing a single instrument at multiple sites, in order to make the most of the instrument's functions, it is necessary to determine channel assignments taking into account the features and constraints of each function. Points to consider when determining assignments are summarized for each instrument below. This section explains the functional constraints and points to note for each of the following instruments. This will cover TSM, PSQ, Threading Mode, and DSSC in the HSD-32. In addition to these, the HSD-64, the successor to the HSD-32, also explains the DIB Access matrix. The presentation will cover how alarms that occur on a TMU, APEx, or bank basis are handled in the UPD-64. It will also cover APEx and Common-Low connections for each bank in the APU-32A. This will also include channel pairing using AB Mux in the SPU-8112.

When preparing the test solution for an image sensor device the most challenging task is to determine the calculation power needed for fully executing the algorithms in background and saving the image files. Image sensor devices can be several tens of Mpixels in size and the solution may need to test 30 to 40 devices in parallel. Also, the complexity of the algorithms is growing driven by the need to guarantee a higher quality of the captured image. The DSP computer receives the image planes from the capture instrumentation and must execute the algorithms in real time. So that no overhead will be seen in the main test program run. DSP instrumentation and DSP licenses can be expensive. A proper sizing of the calculation needs allows to minimize the cost of test and avoid having delays on the production line. In this paper we will show how to use the image sensor device info to decide the number of DSP computers needed and the number of licenses to be activated.

The use of imaging devices is growing year after year. We can find imaging devices in our computers, telephone, car, home control systems, industrial devices, etc. On top of the number of image sensors also the size of the sensors is growing which is creating new challenges for the Automatic Test Equipment. The automatic test of image sensor requires, on top of the standard test features, the possibility to save the images planes into files that must be archived and made available for a certain time. Collecting the files and transferring them to a server can be a headache if the tester doesn’t provide the needed HW and SW architecture to make is transparent for the end user. In this paper we will show the state-of-the art of the current implementation on the IPQ8 tester and share the guidelines on how the engineer can plan the hardware configuration needed based on the DUT information

When chip-on-chip, chip-by-chip or other monolithic ICs would allow concurrent testing, but the tester’s digital pattern generator is busy with running long ATPG patterns, there is no possibility left to provide SPI/JTAG etc. commands to put the analog part into test modes. The proposed approach allows the uploading of command sequences for various serial/parallel protocols into a controller (e.g., during UserInit()) and then sending them to the DUT at e.g., PSQ/MCU clock pulses or at I2C commands, allowing the analog parts to be put into test modes and so enabling them to be tested concurrently during ATPG pattern runs. The solution utilizes a micro-controller with an I2C slave and several master interfaces as well as level shifters and some glue logic with pass-through mode for digital signals. It can be implemented as a module supporting one or more sites depending on the selected micro-controller.

Recent improvements in ML capabilities allow addressing a greater range of semiconductor test problems with higher confidence levels, moving ML models into the toolbox for Test and Product Engineers. Different ML models, of course, perform different functions. Some examples include: * Regression Models for curve fitting , used for reducing the number of measurements required to optimize register settings for minimum operating voltage (Vmin) test, and adjusting search ranges and step sizes for faster calibration of various analog functions. ML models can do multi-dimensional regression on many parameters at once. * Outlier (or “Novelty”) Detection Models can be used for Part Average Testing (PAT) and Dynamic-PAT, which means using the statistics of each lot or wafer to tighten the test limits for high reliability testing, such as automotive, medical, or military devices. It may also be used for detecting a process shift across wafers or lots, and even detecting DIB, probecard or socket issues during test. * Classification Models can be used for things like Speed Binning digital devices, and for automatically classifying Wafer Test Defect Maps and Schmoo Plots, as well as enabling or disabling tests based upon test results earlier in the test flow (i.e. Adaptive Test). Customers want to implement ML in test in order to reduce cost of test by reducing test time through adaptive test and predictive calibration. But since ML calculations are often very compute-intensive, running their models on the tester host computer would be counter-productive. They need a well-integrated parallel processor with software support in the host programming language - IG-XL for now, MST and others to come. They also need high IP security for both their ML models and their data. Built-in multi-site ML support such as python, scikit-learn, and Docker containers facilitate ease of use. Containers are lightweight alternatives to Virtual Machines (VMs). While VMs emulate an entire operating system (OS), containers share the host machine's Kernal, resulting in smaller file sizes, faster startup and operation, while still offering process-level isolation and portability. On the UltraEdge, containers allow the user to use any desired programming language (or specific version thereof) that will run on a Linux core, bundled with their program and all of its dependencies, eliminating version conflicts when deployed to production sites around the world. Come learn what Docker containers and images are, how to develop and build them for your production Machine Learning application, and how to download and use them on the UltraEdge for a seamless production deployment.

The semiconductor wafer test market is trending toward higher pin count devices requiring more connections within the probe card architecture. In addition, UltraFLEXplus provides the capability for increased parallel testing for some devices. This increase in device connections directly contributes to increased probe force over larger probe array areas. Probe force management on the UltraFLEXplus platforms is addressed in multiple areas: The probe card architecture, the docking interface architecture, and the tester’s frame architecture. The UltraFLEXplus probe card architecture is structurally compatible for these high force applications. UltraFLEXplus can effectively manage many probe applications used today up to 150Kg. This paper will address new features focusing on probe force application requirements beyond 150Kg. These new features will be introduced with their respective rigidity contributions for managing high probe force applications for all devices regardless of parallelism at wafer test. This upgrade approach will increase the overall force management performance used with all the UltraFLEXplus platforms for wafer testing.

Emulating production environments presents significant challenges, particularly regarding the needs of probers and handlers. This paper introduces a versatile software solution designed to emulate the GPIB system on any Teradyne platform. This agnostic software can read various types of log files and replaces the NI GPIB library to send accurate responses based on the created logs. We will explore multiple use cases, including enhancing driver development, implementing regression and reliability tests, and testing products such as TEMS in production modes within a "production emulation environment." Additionally, this software aids product engineers in testing their programs in customer production environments. The emulator facilitates testing of tester software, various products, and accelerates the deployment of test programs in customer production settings.

SiPMs (silicon photomultipliers) are single-photon-sensitive devices based on single-photon avalanche diodes (SPADs) implemented on common silicon substrate, it generates pulses after absorbing photons. Major advantages of the SiPMs include wide detection range, high gain, high sensitivity (down to a single photon) , low bias voltage, and no magnetic field interference. These characteristics make it a good choice for light detection applications, for example time of flight positron emission tomography (TOF-PET), distance measurements in LIDAR applications, quantum-cryptography and related applications. In SiPMs soc testing, ATE is usually required to provide illuminator, force high positive or negative voltage as device bias voltage, make current measurement and count the device output pulses at high frequencies. This document introduces the SiPMs test solution on Teradyne IP750 platform. APMU is a power supply instrument of IP750, the test solution takes advantage of APMU’s high voltage ranges as well as greater current capabilities. HSD800 frequency counter is used for counting the pulses, how to setup it to co-work with digital channels of different timing mode is introduced.