Teradyne Users Group

TUGx Global Seminars are a series of one day, free events held throughout the world both in-person and virtually. These local seminars provide an avenue for Teradyne to share best practices and new test methodologies, ensuring content is relevant to the local audience and empowering our customers to get the most out of their Teradyne technology.



Advanced Digital

UltraFLEXplus DCVS Alarm Setting to Avoid Burned Probe Cards
Original Author: Robert Lin
During wafer probe testing there was a situation in which a probe card burned twice in two weeks. We determined that the root cause was the high current functional tests. To resolve the issue we collected current profiles for all functional items so that the designer could analyze and provide updated device settings for some of the high current test items. In addition, we also adjusted the programmed settings of the UVS64 to reduce the duration of any over current events. This presentation we will review the DCVS programming features which can be used to reduce the likelihood of a burned probe card, including VSlewRate in Pin Levels sheet, DCVS Behavior, Fold, and Timeout Settings and power off sequencing.
Understanding UltraFLEXplus Specifications
Original Author: Mike Patnode
Teradyne tester specifications list instrument capabilities and limitations, and the accuracy of instrument parameters. Words like guaranteed, typical, and measured are defined by the specifications, and manufacturing each instrument includes measuring the values noted in the specifications. Using the UltraFLEXplus as an example, this presentation will address what is specified, and what is not, and review the specified calibration process to ensure specified parameters continue to be accurate, enabling the user to design accurate testing and guide them to appropriate guard banding.
Efficient Jitter Measurements of Low Frequency Asynchronous Clock Outputs on the UltraFLEX Family
Original Author: Leo Di Bello
Devices with interfaces like Ethernet (RMII) that also work with 10/100 Mbps speed require a relatively low 25/50MHz clock output. The clock, in most cases, is generated either from an external crystal, or an internal or external clock generator that runs asynchronously to the tester clock. Besides measuring the frequency of those output clocks, it is also necessary to measure the Random Jitter (RMS Rj). The UltraFLEX family offers a fast Walking Strobe measurement capability on the UP1600 and UP2200 to measure the random jitter (Rj) as well as data dependent jitter (DDJ) of output signal edges. Unfortunately, a clock period that is a few picoseconds faster or slower than the expected period, can cause the measurement to fail, especially when many sites need to be tested in parallel, since each crystal has a slightly different frequency. This presentation will demonstrate some limitations when measuring Rj jitter on low frequency clocks using the Walking Strobe method. It will provide possible methods on how to test sites in parallel with an efficient test time using different setups and methods. Finally, it will compare the different methods in terms of accuracy and test time.
112Gbps PAM4 and NRZ PHY Layer Testing Using Third Party Instruments
Original Author: Timothy Lyons
Network processors, infrastructure networking, and backbone IT data farms are leading the charge in applying FEC encoding and active equalization to PAM and NRZ SERDES channels to achieve the next round of step function improvements for data rates at 56Gbps, 112Gbps and even >200Gbps over single channel copper. Automotive, imaging, and consumer are not far behind. With this new technology, the industry is demanding ATE-based test capability. This presentation will discuss the results of a “level 0” integration of third-party hardware, software and signal delivery to provide lab quality near DUT source and measurement capability. The solution described will include BERT drive and receive up to 56Gbaud, and an exciting oscilloscope-like capability through a high performance DSO from Multilane. The challenges overcome will be described and the real performance capability achieved will be demonstrated. The presentation will also discuss the tradeoffs between performance PHY testing and “low protocol” functional test, along with a strategy for transitioning between the two testing types discussed.
Alarms Reporting, Processing and Debugging on UltraFLEXplus
Original Author: Jacques Vieuxloup
Alarms are a key component of Teradyne’s test systems. They indicate a hardware condition caused by a bad device, an incorrectly programmed instrument, or a test system failure that may invalidate a measurement, potentially causing a bad device to be sorted as a bin1. The UltraFLEX tester family has implemented a fully-integrated Alarm Service that ensures hardware alarm conditions are monitored, filtered, reported and processed properly without requiring additional user code to the test program. The user can then choose to have the device binned either to the fail bin associated with the alarming test or to a dedicated alarm bin. The UltraFLEXplus and its PACE pipeline architecture introduced nuances in the way alarms are handled. This presentation will describe how the alarms reporting and processing work, present different debugging tools and review best programming practices.
Implementing and Debugging the Serial Wire Debug Interface
Original Author: Gavin Shang
Serial Wire Debug (SWD) is a 2-pin electrical alternative JTAG interface that uses the same JTAG protocol on top. SWD uses an ARM CPU standard bi-directional wire protocol, defined in the ARM Debug interface V5, enabling the debugger to become another AMBA bus master with access to system memory and peripheral or debug registers. SWD uses fewer pins than JTAG, but has a higher transfer rate and is more stable. It is a useful interface for ARM devices or IP core testing and is gaining acceptance as the preferred interface for firmware burning. This presentation will introduce the SWD interface protocol, describe how to implement it by pattern and offer tips for online debugging.
Introducing Repeatable Code Sequences on the UltraFLEXplus
Original Author: Daniel Murphy
A common requirement of ATE device test solutions is to provide tight timing repeatability across a sequence of tester actions. This capability is needed to meet device specs, optimize test time or maximize yield. The usage varies widely across device types and test blocks within a program, and often spans analog and digital tester resources. The Parallel Advanced Command Execution (PACE) architecture, unique to the UltraFLEXplus, provides an exclusive approach to a repeatable test sequence while being extremely easy to implement. With only two lines of additional code, a section of tester commands can be set as a “Repeatable Code Sequence” block. Another important benefit is that the development and production environments all use the same implementation and behavior, facilitating debug and correlation by not introducing different modes, which is not possible with solutions that develop and debug in a code approach but convert to a pattern-based approach for production. In this presentation, you will learn about this new capability, available in IG-XL 10.30.00, which can work seamlessly with the PACE architecture to preserve the test time optimization already provided by the system.
Fast Throughput on the UltraFLEXplus Enabled by the PACE Architecture and Site-Aware Variables
Original Author: Bill Davis
The introduction of the UltraFLEXplus has shifted the paradigm of testers to enable faster communication and throughput via the Parallel Advanced Command Execution (PACE) architecture. However, even experienced users assume this new architecture is an extension of the legacy “data backgrounding” capability of the UltraFLEX and DSP PCs, however it’s not. The controller PC workstation works in concert with enterprise network processors onboard the instrumentation to pipeline tester interaction into multiple, distinct communication channels. Command, results, alarms, datalogging, and DSP processing all execute from their own threads. Unlocking this potential throughput improvement does not requires highly complex code practices. Using native site-aware variables that are part of the VBT code base, IG-XL takes advantage of the parallel computing and communication environment while retaining a simple programming model to ensure fast multi-site test program bring-up. In this presentation the conjunction of easy coding and fast performance will be demonstrated, along with examples of improving code to eliminate differences between single site and multi-site programming.
Keeping Devices Cool
Original Author: Carl Peach
Device cooling is receiving renewed interest as large digital devices become more commonplace in applications such as Artificial Intelligence (AI), Machine Learning (ML), and non-battery based applications. We’ve seen processor technology evolve over the years from air cooling to liquid-based cooling to device-responsive cooling, however some of the objectives of cooling remain elusive due to the proximity of thermal sensing, cooling techniques, and device packaging. This presentation will discuss the objectives of device cooling, specifically, avoiding front-end hardware damage and yield improvement, as well as some of the obstacles to maintaining a constant temperature at the transistor junction (thermal mass, time constants, effect of different cooling media). Additionally, the Automatic Thermal Control (ATC) cable option for the UltraFLEXplus will be reviewed to demonstrate its capabilities, and how to use this interface to communicate with external thermal equipment.
Saving Vector Memory on the UP2200 with Functional Vector Compression
Original Author: Christopher Cassidy
Digital devices continue to grow the need for vector memory. While scan patterns often consume the bulk of the vector memory used by a test program, functional patterns can still comprise a significant portion of overall vector memory. Teradyne’s UltraFLEXPlus UltraPin2200 and UltraPin2200+ enables memory sharing across 16 channels, and to further aid in making the best use of the instrument’s vector memory, IG-XL 10.30.10 is adding three new features that can reduce the size of a functional pattern. These features include two new pin setups, allowing the declaration of pins as input or output only through a pattern, which reduces usable states for pins while saving memory. Alongside these pin setups are two features to aid in implementing SCAN memory savings into parallel patterns easier, including a new syntax that aligns SCAN blocks to parallel vectors, and flexible scan, which allows the use of a subset of defined SCAN pins in each SCAN block. This presentation will give an overview of these new features, outlining how to use them, when they are most useful, and their limitations.
Improving Multi-site Efficiency with Independent Patterns per Site
Original Author: Matthew Tilleman
Test solutions use many different techniques for improving throughput, reducing test time, and ultimately lowering the cost of test. The most fundamental of these techniques is to test multiple devices in parallel but as adaptive test methods seek to optimize the yields of increasingly complex devices, the throughput benefits of multi-site testing may be reduced. Different devices may not only require unique power or timing settings but may also need to execute different sets of pattern vectors. This last requirement has historically required that sites run serially, resulting in increased multi-site test overhead. This presentation will demonstrate how to leverage the hardware and software features of the UltraFLEXplus tester to improve multi-site test efficiency by running different patterns simultaneously on different devices. The key enablers of this capability are the highly flexible architecture of the UltraPin2200’s independent pattern generators, as well as new software features that present simplified programming models for executing different patterns per site. The presentation will also explore extended capabilities, such as CPU loops and instrument operations.
MPD Bus/Interface Characterization With or Without Source-Synchronous Hardware on UltraFLEX
Original Author: Dayuan Lin
For a custom Parallel Data (MPD) bus/interface, the differential clock output from the DUT and the 28bit parallel data output pins from the DUT at 1000Mbps have a source-synchronous relationship. Classical functional testing methodologies do not account for such characteristics and as a result, if the standard test comparators on fixed edge in the vector is used the output data may fail the requirement. Source synchronous testing provides an effective method for eliminating phase and voltage jitter by using both clock and data signals from a DUT. This presentation will describe the precondition of source synchronous uses and DIB design, UltraPin1600 channel selection guidelines and the test requirements of MPD for this case. We’ll also compare the standard functional test with a workaround method of using customized multiple time sets of strobes, with source-synchronous to collect clock reference offset and output data voh/vol parameter for capturing and post-processing to check the shmoo eye. Finally, we’ll compare and contrast the stability and efficiency with and without source-synchronous.
Using TestInsight to Convert High Speed Scan STIL to UltraFLEX/UltraFLEXplus Patterns
Original Author: Vivian Wang
Advanced processes are driving rapid growth in testing with a need for new approaches to testing at higher speeds. High-speed scan testing for IEEE 1149.10 has provided one option. Serial scan testing requires a handshake between the high speed serial and JTAG ports, which has introduced challenges for traditional ATE test methods. Dual time domains for high-speed serial lanes and setup patterns are required to start both together or to execute one while the other one is in keepalive. In cooperation with the electronic design automation (EDA) vendor Siemens Mentor and the ATE Software vendor Test Insight, Teradyne has created a test solution for our tester platforms. This presentation will discuss the challenges of serial scan testing and review the TestInsight ATEGen software solution for IEEE 1149.10 pattern generation to convert Mentor STIL files to ASCII pattern files on the UltraFLEX and UltraFLEXplus testers.
Current Profiling: In a Class of Its Own
Original Author: Kitty Belling
One of the most helpful debugging aids is a clear picture of what’s occurring at a given point of failure. In the case of power instruments, this clarity can come from a current profile of a failing or alarming power supply. A current profile shows the measured behavior of the loads on a device, which makes it an important tool for identifying major current draws and spikes. With this information, test engineers can correlate on-tester device performance with the  designer's expectations. This is true both for a big-picture view of the entire program and for a closer look at a pattern. This presentation is a companion guide to a Visual Basic class module that serves as a tool for collecting current and voltage profiles. This tool can be used to create a profile using any DCVI or DCVS instrument, such as the UVI80 or the UVS256, and can be imported into IG-XL test programs, adding code wrappers around the code to be profile. The class then stitches the collected profiles together and outputs a single profile of all wrapped sections of the test program, as well as optional individual profiles. This presentation will demonstrate how to use the tool, as well as best practices and useful tips.
Understanding the Test Challenges of SCAN Using 1149.10 and How UltraPin2200 Solves Them
Original Author: Dwayne Dohmann
Scan has always been a key test item for SoC devices. With the ever-increasing number of gates, the test time for scan continues to increase. Customers face tough decisions weighing test time versus coverage. Increasing the scan bandwidth can be used to counter the ever-growing scan requirements but before considering how to increase this, customers must also consider other complexities. Complex hierarchies create challenges to implement the DFT required for scan. Additionally, the constraints on the number of pins available compounds the complexities, all of which points to a need to find new approaches to reduce the complexity and counter test time. One approach stems from IEEE 1149.10 specifications, in which Siemens has developed a solution using their Streaming Scan Network to achieve scan over SerDes. This presentation will explore the implementation Siemens has created for IEEE 1149.10, the test challenges and how UltraPin2200’s unique architecture solves them.
Using a DUT’s HSIO Interfaces in a Fully-Functional Protocol Configuration for SCAN Test
Original Author: Troy Zhang
Advanced Digital Devices are experiencing exponentially increasing test challenges from multiple directions. The industry is responding by introducing new approaches to test that expect to disrupt the status quo. One key area of opportunity is in scan and structural test, with a number of emerging options that will improve efficiency and effectiveness. With more transistors to test and new failure modes due to advanced technologies, the amount of total test data volume continues to grow at an exponential pace. The existing standard approaches to DFT structural testing, such as scan, have encountered practical limits, in part due to data bandwidth from limited GPIO rates and limited or fewer pins available for scan. One of the new leading options to overcome these limitations is to utilize existing High-Speed I/O interfaces, which promises to provide much higher test data bandwidth while also reducing the number of digital test pins required. In addition, it offers exciting new opportunities such as leveraging the ability to perform DFT test across the silicon lifecycle, from ATE through System Level Test (SLT), and even through to the final in-field environment. This presentation will explore the benefits and test considerations of using HSIO interfaces in their fully-functional protocol configuration for structural test. It will describe Teradyne's strong development partnership with Synopsys for their DesignWare HSAT and Test MAX ALE products, and how we are enabling the most advanced test solutions for the future of protocol-based test.
Pattern Compilation Multithreading
Original Author: Christopher Cassidy
Large test programs can contain thousands of patterns and compiling ASCII patterns to the binary pattern file format using the Windows Pattern Compiler can takes hours if not days. The extensive time spent on compilation is often caused by two factors. First, the single-threaded nature of the pattern compiler, where patterns are processed one at a time, resulting in the underutilization of resources on computers with multiple cores. Second, the overhead introduced by waiting for the pattern compiler to start up before compilation and close out after compilation, resulting in a significant amount of overhead time spent for each pattern. Creating a code function or script to wrap around the Pattern Compiler Command Line Interface allows for flexibility in the usage of the tool, creating opportunities for significant improvements in the tool performance. This presentation will discuss best practices for wrapping a command line tool, multithreading the pattern compiler to process multiple files simultaneously, and how best to reduce overhead between compilations.
Tester Performance Challenges for WiFi7
Original Author: Ken Lanier
WiFi7 and new cellular standards will create additional challenges for testers and test strategies. Testers will need to measure higher and higher levels of performance, while lowering cost of test through higher tester throughput. This presentation will discuss new architectures for RF instruments being deployed and how new DFT strategies are being employed to simplify test and reduce costs.


ETS-800 QMS Measurement Accuracy Improvement for BMS & POL Applications
Original Author: Brian Foley
Battery Management Systems (BMS) using Li-Ion batteries are driving toward the ability to measure voltage and current at ever tighter tolerances. The more accurate the measurement, the more accurate the State of Charge (SoC) or in the case of an Electric Vehicle Distance to Empty (DTE). This has pushed differential cell voltage measurement accuracy requirements down to 100uV in a 5V range. The QMS has excellent resolution and accuracy but needs to be tighter for future BMS test requirements. The goal is to reduce the offset and gain errors of the QMS allowing for a ±100uV or better short-term measurement accuracy. This presentation will detail the methods used on the ETS-800 to improve its short-term accuracy, including evaluating a reduction in the specified temperature range of ±5֩C and enabling an Auto-Cal procedure for the QMS when its temperature drifts from a specified limit. We’ll also discuss how the QMS’s 5V measurement accuracy will be verified using a High Precision Voltage Reference ±(0.3 uV/V at 30 days), Noise ±(0.06 uV/V rms) and Temperature Coefficient ±(0.04 uV/V per ֩C).
12 Cell BMS Test Solution for the ETS88
Original Author: Tarzan Lin
In recent years the electric car market has exploded across the world with one of the key components being the battery. As battery importance increases, Battery Management System (BMS) devices are evolving to make the battery work more effectively. The ability to use existing test equipment to test BMS devices in production will enable faster time to market. This presentation will discuss techniques for using of the ETS-88 tester to test BMS devices, with a focus on a low cost ETS-88 configuration that requires no external circuit, has floating resource flexibility and a highly accurate QMS.
Spike Check Automation Tool for Automating the Oscilloscope and ATE Operation
Original Author: Rui Wang
Automotive and power management device testing requires extensive quality checks, including ensuring that the intended test conditions are applied so that each device under test (DUT) pin is driven with the intended voltage waveforms. This testing step must not expose the DUT pins to voltages outside its absolute maximum ratings (AMR) or to voltage and current spikes. Checking for these is a time-consuming process which often adds to development time. In this presentation, we’ll discuss the Spike Check Automation Tool, available for the ETS-800 and UltraFLEX platforms, as an effective way to automate the oscilloscope and ATE operation to systematically capture the waveforms on the relevant DUT pins and generate reports to makes the spike analysis and waveform documentation simpler and faster.
Using the Remote Connectivity Matrix to Enhance Test Program Debugging in a Remote Environment
Original Author: Daniel Gray
In a global economy, the ability to work remotely, effectively and efficiently is crucial to completing projects on time. With the onset of the COVID19 pandemic, the demand for remote access to tester hardware and network-connected devices has greatly increased. While tester PCs, oscilloscopes and other device software is accessible through network infrastructure, hardware debug still requires a hands-on approach. Even to examine a signal, a person needs to physically place a probe on a test point to view it on an oscilloscope, and remote work can be limited by the reality that oscilloscopes are limited to four channels in many cases. Additionally, when debugging onsite, moving probes is time consuming, and in some cases signals may not be accessible if the test head is docked to a prober or handler. The Remote Connectivity Matrix (RCM) was developed to address this limitation. In this presentation, we’ll discuss the RCM, a remotely controllable relay matrix designed in a compact and modular box that can reliably wire hundreds of DUT signals to an oscilloscope. Coupled with DIB design, this tool allows the test engineer to remotely debug a test solution without the need to move probes and increases debugging efficiency in a global, remote environment. The RCM also interfaces with Teradyne’s SpikeCheck Automation Tool to greatly reduce the engineering time required during product release. Attend this presentation to learn more about the RCM, a valuable tool for debugging hardware and test programs in an increasingly remote, global economy.
ETS-800 Test Program Checking Tools Overview
Original Author: Eiichiro Machi
Often multiple engineers work on one test program with shared debugging of device test blocks. This can result in program quality issues, such as inappropriate instrument setting or instrument meter range usage, due to skill level gaps, causing additional work and resulting in schedule impacts or cost increases. To prevent these types of problems during the test program development phase, Teradyne has developed several tools to ensure program quality. This presentation will discuss the tester setting readback tool and the instrument range check tool, both utilizing a software structure that is directly linked to the test program. The readback tool generates an ASCII exported file at the instrument DC measurement timing, such as SPU/APU/HPD/HSD mi/mv during program execution. It also supports HSD/UPD time stamper measurement and digital functional tests. The instrument range check tool similarly generates an ASCII exported file at the instrument DC measurement timing. For post processing, an Excel macro calculates if the instrument range setting is appropriate for the test limit based on the instrument specification.
TDR Offset Automated Collection on ETS-800
Original Author: Luffy Jin
Delays caused by transmission lines bring unwanted effects particularly in critical timing tests where the specification ranges from a few nanoseconds to tens of nanoseconds. Teradyne’s MST2021B includes a new feature that enables HSD32 to support automated offset measurement, however for previous versions of MST the user needs to collect the offset manually, which is not reliable and therefore unacceptable in production. In this session, we’ll demonstrate a method for measuring Time Domain Reflectometry (TDR) by repeatedly bursting a digital pattern that contains customized edgesets and a binary search algorithm to achieve a self-drive and self-strobe edge search process to acquire the offset value. It can be executed in UserInit so that it does not impact test time, and can be executed only once per hardware, with the offsets saved to a tdr file. It can be implemented on both HSD32 and UPD64 if the transmission line is valid to form the reflectometry. We also discuss pin to pin delay tests in a real-world application.
Teradyne Productivity Tools for EV-MST
Original Author: Massimo Zambusi
Time to market and remote debugging efficiency are two of the most common requirements for test engineers, especially given the events of the past two years. ATE platform software provides a consistent development and debug environment, and regular updates and enhancements but its development and quality assurance cycle time makes lower priority features or customizations hard to ontain in the short term. Teradyne has allocated dedicated application engineering and a software team devoted to designing and maintaining a suite of tools which enhances the test engineer’s experience and complements the core platform software. Over the past five years these tools have grown, starting from a few simple tools to a wide set of powerful tools and code extension libraries. This presentation will provide an overview of the main existing and upcoming tools, including the well-known TerMSTApp, MST TP Skeleton Generator, ShowTool, ShmooTool and Timelines, and their amazing new features. We will also cover recently deployed tools like the Remote Connectivity Matrix and Virtual Scope, focused on remote access to the oscilloscope, and provide a sneak preview of the soon to be released tools: Pattern Quality Assurance, Spike Check Automation, Advanced PinMap Entry, and ShowTool DutView reporting. Learn how to access these tools conveniently through the Productivity Tools Toolbar, as well as eKnowledge.
ETS-800 All-In-One Threshold Test Methods
Original Author: Cham Li
In 2018, we delivered a presentation about different threshold test methods on the ETS-800 platform. With the upgraded HRM instruments, UPD64, APU32A and MST version, there are more highly efficient choices. This presentation will summarize newly available test methods utilizing the new features of these instruments. Additionally, we’ll discuss a code library as .h/.cpp files which combines different threshold test methods into a single test function so that a user can configure or switch them easily. It supports various instrument combinations and debug display, making our development easier and more flexible. Users can save time developing and debugging manual code after a one-time study, and leverage it in future projects to speed up test development.
Test Time Analysis of DSSC on the ETS-800
Original Author: Daniel Marsh
Digital Signal Source and Capture (DSSC) is a powerful feature on the ETS-800’s HSD-32 instrument. It enables the reallocation of digital pattern memory while the test application is running. The ability to change digital pattern memory “on-the-fly” accommodates the dynamic memory needs of complex devices. This presentation will discuss a brief overview of the feature and then delve into the test time implications for different modes of operation, including read and write capability in both parallel and serial modes. We will review multiple use cases and the corresponding DSSC settings to achieve the fastest test time.
Power Management: Protecting Today’s Sensitive DUTs
Original Author: Doug Pounds
Today’s Integrated Circuit (IC) devices have smaller geometries and lower voltages. As such, maximum voltage ratings are getting smaller and more sensitive to electrical over stress (EOS). This is further complicated by smaller differences between the working voltage of an IC device under test (DUT) and the maximum voltage the DUT can tolerate. Traditional Tester VI Kelvin run away protection may not be sufficient to protect the IC or DUT for production test. It is not unusual when a Sense path connection is lost, due to a poor contact, that the forcing voltage or forcing current will exceed the DUT maximum voltage rating and electrically over stress the DUT. This presentation will discuss a variety of different Kelvin run away and clamping methods to protect the DUT in cases with poor contact during production testing. These techniques are test platform agnostic but will be shown relative to the ETS-800 instruments.
Automotive Trends and the Effects on Semiconductors
Original Author: Aik-Moh Ng
The automotive industry is undergoing seismic changes under our feet. Shared self-charging, connected, driverless automobiles will fill the streets, replacing traditional vehicles. Soon internal combustion engines (ICE) will be a thing of the past. This session will discuss the new trends in automotive driving significant growth in semiconductors.


Memory Tester Automation, Data Aggregation and Post Processing
Original Author: Mark Gilson
Memory test infrastructure and the way in which tests are streamlined have been advancing rapidly with the use of automation. This presentation will detail a method by which a Teradyne Magnum V tester is automated using open-source software, Jenkins, to control and streamline calibration and test execution through the tester’s command line interface, reducing human interaction and enabling continuous test execution, and data collection and processing. With this configuration, tests can be run on a scheduled basis, based on firmware changes by monitoring the source code repository, at any time of the day, or based on a user request. Results can then be rapidly analyzed and distributed nearly immediately following the completion of testing, and users can be notified of test results and completion through custom email alerts. With this setup, more testing is possible with less effort due to the offloading of redundant tasks, which automation software aids in completing.
Application PAM-4 Test Solution for GDDR7
Original Author: Sung-Taeck Jung
PAM-4 signaling is being standardized for GDDR7 and a near-term application solution to test GDDR7 devices is needed for Teradyne’s Magnum-EPIC tester with multiplexed NRZ signaling, until a native PAM-4 feature is available in Teradyne’s next generation tester. The biggest change in the transition from NRZ signaling to PAM4 is the availability of three eye diagrams instead of one, and the need to be aware of the relative positions and shapes of all three eyes – upper, middle, and lower. This presentation details a proof-of-concept DSA solution that includes scope jacks, loopbacks and AWG inputs to the tester channels with various lengths of traces. We will review techniques applied to program 4 PAM-4 symbols and API suggestions for the symbol programming method of 4 different drive levels, with supporting scope waveform data at various Baud rates. We will also cover the challenges to test three different levels of the PAM-4 output eyes and propose a solution for how to judge test results with loopback eye shmoo data. Lastly we will discuss other challenges with this solution at a higher data rate, 7G Baud for example, and enhancement ideas for better performance and improved productivity.
Application Vector Test Solution for GDDR6
Original Author: Sung-Taeck Jung
In general, memory test equipment uses ALPG to create and use repetitive and sequential addresses, with predictable and arithmetic values also used for the data put into the address. Instead of sequential or repetitive addresses, users access random addresses, and often, they write or read random data. Therefore, information about defects is primarily provided in the form of a random vector rather than a traditional memory test pattern. If vector memory is supported by the memory tester, the provided random vector type of failed information is tested by implementing the random failed information as it is. However, Magnum EPIC testers only support subroutine memory. This presentation will detail how to perform a limited vector test using subroutine memory on a Magnum EPIC tester without vector memory. We will discuss the tester's resource allocation in the process of converting a general vector to subroutine memory and points to be aware of, and an example of actual GDDR6 device testing.
OpenXLSX: An Open Source Replacement for the Magnum Excel OLE API Layer
Original Author: Ross Youngblood
On MagnumV testers, OpenXLSX, an open-source alternative to Microsoft Excel, was successfully evaluated for applications where reading/writing to an Excel file from a user test program or custom GUI tool is the desired solution. This presentation will demonstrate the basic open/close calls of XLSX, how to build Visual Studio 2019 solution files with CMAKE, and compare its read/write performance to the existing Magnum Microsoft OLE calls for *.xls and *.xlsx files. Magnum users using Visual Studio 2013 or Visual Studio 2019 and interested in using other open source libraries with Magnum systems (zlib/pcre/crypto) will learn how CMAKE is used to create Visual Studio build environments and build *.lib/*.dll libraries for use with Magnum test programs.
Visual Studio 2019 & MSbuild Tips and Techniques for Magnum Users
Original Author: Ross Youngblood
The Magnum tester platforms are programmed in C/C++ using the Visual Studio IDE. This presentation will present a migration path to Visual Studio 2019 and H4.x/H8.x software for those using older versions. We’ll cover important tips and tricks to get the most out of Visual Studio 2019 learned from several years of migrating customer code from the legacy VS6.0 environment to Visual Studio 2013/2019. We’ll focus specifically on build speedup options, and how to manage/deploy custom libraries in environments where both MagnumV and newer test systems will co-exist on a test flow with Magnum 2/2x systems running H7.x/H8.x. We’ll discuss how to install “Side by Side” installs of Visual Studio in cases where a different version is required for other non-Magnum development work, and the integrated GIT support in Visual Studio 2019 and Visual Studio 2022 for those using GIT for source revision control. We will also focus on the multiple build speedup options in Visual Studio, multi-processor builds and pre-compiled headers, and how to manage these within a Magnum build environment.

Image Sensor

2.5Gbps CIS Device Testing with an X-ECU Solution
Original Author: Tracy Wang
MIPI D-PHY 2.5Gbps has become the trend in the current image sensor market, with requirements for capturing images under 2.5Gbps or even higher test rates, instead of the 1.5Gbps image capture speed used previously. This presentation will introduce a method for 2.5Gbps image capture in CP mass production with the X-ECU solution on Teradyne’s IP750, including a review of an actual project for both hardware and program development. For the hardware, we will discuss the key points related to the PIB and probe card design, as well as the integration of the external X-ECU system and the tester. For program development, we will discuss the actual capture waveform at X-ECU from 1.5Gbps to 2.5Gbps and the test time comparison with and without X-ECU. The basic programming steps and multi-site debug skills will be also detailed.
How to Develop a Customized DLL in the IP750 IDP Add-in Library
Original Author: Triston Ma
The IP750 IDP add-in is an environment for developing an image processing library (IDP Add-in Library). It enables the creation of a customized image processing function without modifying IG-XL source code in the IDP add-in and the add-in functions can be executed in a multi-threaded environment without coding a multi-threaded unique process. The IDP Add-in Library has some API functions that Teradyne has provided for add-in development but users could also develop their own functions to either implement more common image data processing or adopt special algorithms for image data analysis in the IDP Add-in Library. However, if there is a need to maintain confidentiality of a custom algorithm a specific implementation of the algorithm will be required by calling a custom DLL in the IDP Add-in Library. This presentation will describe how to develop a customized DLL that could be invoked in the IP750 IDP Add-in Library and how to debug it in Microsoft Visual Studio IDE when IG-XL is running.
An IP750 Rear Shift Docking Solution
Original Author: Kazuhiko Takayama
In the IP750 tester, there is a need for a wide illumination area to test large image sensor dies with higher site count coverage. To satisfy this need, Teradyne had developed twin direct docking, which rotates the test head together with the illuminator and LBox . Our newest docking solution for the IP-750ExHD provides a wider illumination area and can be better adapted to multi-site image sensor testing. In this presentation, we will explain the benefits of the rear-shift docking compared to the existing docking solution, and best practices for how to integrate the test head and the prober to maintain signal integrity.
Image Sensor Protocol Updates
Original Author: Naohiko Irikiin
It has been more than 13 years since Teradyne introduced the MIPI D-PHY solution for the IP750 platform. Since then, MIPI has become the most important industry protocol not only for mobile device applications but also non-mobile applications, and it continues to evolve. This presentation will detail both the logical layer (CSI-2) and physical layer (D-PHY, C-PHY and A-PHY) updates and discuss the SLVS-EC protocol, which is becoming the standard for machine vision applications. We’ll cover PHY technologies including MIPI D-PHY, MIPI C-PHY, MIPI A-PHY and M-PHY. We’ll also cover SLVS-EC, which was originally developed by Sony for their image sensor devices and adopted by EMVA as its standard. SLVS-EC has applications in machine vision.


Examining mmWave Structures using Time Domain Reflectometry
Original Author: Coleman Weaver
Multi-layered, complex mmWave Device Interface Boards (DIBs) are becoming more common as devices start to utilize the 5G millimeter-wave frequency bands and the full capabilities of Teradyne’s microwave extension instrumentation. This complexity causes even the slightest manufacturing variations to result in mmWave performance degradation. A Vector Network Analyzer (VNA) checks to see if this performance degradation exists but does not reveal where the degradation occurs or what could be causing it. Because of this, a need for more diagnostic tools has surfaced. Luckily, a tool often used for high-speed digital trace analysis can help solve this issue: Time-Domain Reflectometry (TDR). By incorporating TDR into your mmWave DIB evaluation process, impedance discontinuities can be precisely found quickly and cost-effectively. This presentation will discuss the benefits and limitations of Time Domain Reflectometry in the context of examining mmWave structures.
Over-the-Air Testing of Radar Devices on the UltraFLEX
Original Author: Mike Carr
Radio detection and ranging (radar) devices are everywhere. From cars to elevators, radar devices detect movement, and keep us from crashing into objects and objects from crashing into us. Radar technology is also used in smart industrial applications, such as the tracking, detecting and mapping of autonomous vehicles found in modern factories. Cost effective, advanced manufacturing techniques have led to radar devices leaving fabrication with antennas on the die, known as antenna in package (AiP). These AiP radar devices present unique test challenges that require a multi-site 60GHz mmWave over-the-air (OTA) test strategy. This presentation will discuss the Hyperion 60GHz UltraFLEX test instrument, as well as an octal-site 60GHz Radar OTA test solution. We will review the x8 DIB mechanics and tester configuration needed to support x8 OTA radar testing including the Hyperion 60GHz Instrument, HSD Protocol Aware SPI interface, and the UPAC and DC80 instruments for the UltraFLEX.
An RF Calibration Method for RF Devices in Production
Original Author: Alex Gong
As wireless frequencies get higher, the trace from test instrument to DUT cannot be ignored. Complicated RF testing fixtures, like RF cables, DIB traces, DIB components and socket needles, have made it hard to get accurate test results, making data correlation, including site to site correlation, EVB to ATE data correlation, and DIB to DIB correlation, complex and difficult. These types of issues result in low yield and repetitive work during production. This presentation will introduce an RF calibration solution for common RF devices, including a calibration procedure and calibration tool. The calibration procedure introduces the pathloss model and explains how to get an accurate pathloss value. We’ll discuss system errors in different scenarios and how to manage them, and introduce a tool to help with RF calibrations in both the lab and production environment.
An Automated Station for Efficient, Repeatable mmWave DIB De-embedding
Original Author: Becca Percy
As the need for 5G and other mmWave testing increases so does the need for efficient device interface board (DIB) de-embedding. Multi-channel, multi-site DIBs have a multitude of paths which need to be de-embedded individually. PCB manufacturing variations can cause each path’s performance to vary significantly, including etching, stack-up dimensions, dielectric variations, and performance variations of individual IC’s. As wavelengths decrease, the described manufacturing variations have an increasing effect on insertion loss and impedance matching, which leads to yield fallout. The typical manual de-embedding process, in which the user disconnects and reconnects cables for each path, becomes increasingly time-consuming and error-prone. Enter the mmWave DIB de-embedding station. A custom-designed GUI controls an integrated UR5e robot, Keysight PNA, power supplies, and logic controllers. This station automates the DIB de-embedding measurements of each complete physical path, from the blindmate tester interface through to the DUT socket pogo pin. This presentation will demonstrate the Automated De-embedding Station including: defining the DIB paths, initial setup, data validation, and generation of two port de-embedding S-parameter files for incorporation into an IG-XL test program.
An UltraLow Phase Noise Square Wave Reference Clock Above the UltraWave24 DUT Clock Maximum Frequency on the UltraFLEX
Original Author: Michael Tubbs
When DUT Clock performance is needed on the UltraFLEX at frequencies significantly higher than the UltraWave24 DUT Clock instrument capability and frequency locked to the tester, an application circuit can be provided to address the issue. For wireless systems, a reference clock is used to frequency lock many functional circuit blocks including Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs) and synthesizers. The overall wireless system performance can be degraded or impaired by phase noise or jitter present on the reference clock. Usually, the device under test (DUT) will have one fixed operating frequency for the reference clock. Further, it is common that the DUT clock input is digital and will experience less jitter on the clock with faster slew rate clock input (e.g., square wave input). This presentation will describe a DIB application solution that provides an ultra-low phase noise, square wave, DUT reference clock signal, frequency locked with the UltraFLEX tester, at two available Vpp amplitudes, at a frequency above the UltraWave24 DUT clock maximum frequency of 105MHz.
Enabling UltraFLEX UltraWaveMX8 Full Two-Port S-Parameters Measurement Capability
Original Author: Wei-Min Zhang
The UltraWaveMX8 instrument extends the capability of the UltraWave24 instrument, enabling automated testing of RF signals beyond the 6GHz band, up to 7.5 GHz for source and measure. The UltraWaveMX8 instrument extension is designed to test 802.11ax devices and 5G cellular devices that operate in the mid-band frequency range. S-Parameters describe the electrical behavior of linear electrical networks when undergoing various steady state stimuli by electrical signals. S-Parameters measurement is important in RF measurement but currently the UltraWaveMX8 instrument doesn’t support it, however the instrument has a directional coupler inside the hardware architecture that makes it possible to implement S-Parameters measurement. In this presentation, we will discuss the application solution that enables full two-port S-Parameters measurement capability, including the calibration methodology with available calibration kits and the calibration algorithm that will generate calibration data for the S-Parameters measurement.
Real World Benchmark of an UltraWaveMX8 Noise Figure Measurement Using the Direct Method
Original Author: Sophia Zhang
RF parameter measuring is always done using an averaging method. Averaging may appear in the software of the post data processing algorithm, in the hardware of the embedded DSP (data signal processing) or in the VBW filter of the spectrum analyzer. Different averaging methodologies will have different effects on the final measurement result, and incorrect averaging may cause several DB data errors, which can result in wasted correlation efforts. This presentation will discuss the averaging methodologies frequently used in RF measurement, their differences and when to use each one, using a real world example of a noise figure measurement on Teradyne’s UltrawaveMX8. Keysight’s spectrum analyzer, N9030, is used as the benchmark, and a direct gain method is implemented for the noise figure. A real-world correlation result will demonstrate how to find excellent noise performance on the MX8, and its suitability for the majority of cases with requirements in the frequency range from 50M to 7.5G Hertz.
High-Speed Multi-Channel ADC/DAC Test
Original Author: Dale Wang
This presentation will discuss ADC/DAC test items of multi-channel and high-frequency, from hundreds of MHz to 7.5GHz, with the UltraWaveMX8 and UltraWave24 instruments. For multi-frequency and multi-channel, we will detail the use of the Balun (Transformer) and switch to share the RF source and receiver, and the use of the low pass filter (LPF) to ensure that the source is not interfering with harmonics and noise. When RF Sourcing to multiple sites, the UltraWave instrument normally splits the MW Synthesizer signal from one front end module per site, to the DUT, in which the DIB is designed as equal in length as possible. Even with these parameters, there is no way to ensure the path loss and skew are the same. We will discuss the MWDIB object compensation method to solve this problem and describe how to use the PERL module to analyze these massive amounts of ADC/DAC data.
Quickly and Correctly Setting the Expected Amplitude of the Receiver for EVM test
Original Author: Jack Chin
In an EVM test, it is important to set the expected amplitude of the receiver correctly. If the expected amplitude setup is higher than the device output power, the test result will be inaccurate, and when the expected amplitude setup is lower than the device output power, it will cause an alarm on the tester. Engineers need to check the expected amplitude of each EVM test because it is difficult to get the expected amplitude test conditions from a test document, and MWReceiver does not have automatic and expected amplitude feature for EVM tests. A mmWave device may have several hundred EVM tests. Setting the expected amplitude of the receiver manually is both time consuming and error prone and sometimes the expected amplitude needs to be modified when a test document is updated. This presentation will discuss a new method for quickly and correctly setting the expected amplitude of the receiver for EVM testing and how this process can be automated for faster time to market.
Best Practices: How to Use the Timeline Tool to Improve TTR
Original Author: Vinson Peng
The ESA Toolkit is a software option available for use with IG-XL on the UltraFLEX, which provides integrated tools for developing RF device tests that require modulated signal generation and measurements using standard wireless communication protocols. In the past, it was difficult to achieve test time reduction (TTR) for test items using ESA but with the Timeline tool each ESA demodulation and overhang time is known, to be used to determine the right TTR approach. This presentation will review three proposals for optimizing the results overhang on specific test items, including modifying the test flow to optimize the DSP computer processing; mitigating dependencies for the DSP Global Variable and using different setup names for ESA; and changing the Hdw.DSP.ExecutionMode at Tssi. Using these three methods, we’ll present a real-world example where we were able to collect relevant test time and achieve a final TTR Result of 15.84- 12.85, which is equal to 2.99 seconds or an 18.8% improvement.
Optimized Measurements for RF Functional Verification of 5G and mmWave Devices Using Signal Processing Techniques
Original Author: Rodney Singleton
Lengthy RF test cycle times have long been the norm in production settings. Gated throughput and lengthier test times are often in large part due to measurements that require difficult inline or offline characterizations and processing to pull out useful data and final metrics to set meaningful production quality gates that are robust. As 5G and mmWave demand drives higher frequencies, increased functionality, and higher channel densities, achieving higher process throughput while maintaining traceability, accuracy and adequate test coverage are keenly important requirements. Key to these requirements is measuring the settling of a modulated RF carrier given programmed behavior that emulates the modulation standards 5G and mmWave testing presents in production. This presentation will explore reducing RF test cycle times by strategically employing the use of signal processing techniques, with a custom IG-XL DSP procedure. Using the Hilbert transform and pin list data handling to reliably establish start and ending points of modulation, signal level settling, frequency settling and detection of undesired signaling (glitches) we are able to standardize product functional verification.
Using Host Threading to Manage DSPWave Data and Reduce Test Time
Original Author: Ross Wu
Conventionally the measured digital data of multi-site in Protocol Aware (PA) on UltraPin2200 captures the data frame and then does the post calculation in a VBT function to output the expected result to the datalog. If there is an installed DSP computer on the UltraFLEXplus, it will calculate and analyze the large amounts of data, saving significant test time and increasing efficiency. However, if the data is a part of consecutive small fragment data and the tester does not have an installed DSP computer, the data calculation will be done by the site loop for the DSPWave computation in the VBT function, resulting in lower PTE and increased test time. This presentation will propose a solution for performing the DSP mode in tlDSPModeAutomatic using the host computer threading to manage the DSPWave data with the VBT DSP procedure module, without site loop instead of tlDSPModeHostDebug with the VBT module. This runs DSP procedures inside the thread on the host computer. In addition, the captured PA data is also directly accessing data from instruments and processing DSPWave with the VBT DSP procedure. This method improves PTE by approximately 15% and saves significant test time in multi-site.
Testing mmWave Transceivers
Original Author: Alex Gong
The 5GNR standard brings new test challenges, higher frequency bands, wider bandwidth and a larger data stream. The structure of the mobile phone has also changed to adapt to these new technologies. This presentation will introduce test solutions for 5G IFIC and RFIC, and provide an overview of mmWave IC testing practices, including the structure of the new TRX device; which items are tested in the lab vs. the production environment; the differences between these devices and traditional transceivers; and how to test them with Teradyne’s instrument. For the IFIC, the modulation bandwidth is up to 400Mhz per component carrier and the data stream increases to more than 7Gbps per lane. This presentation will review how to source and receive the high speed data stream, and encode and decode the MAC and PHY. For the RFIC, beamforming makes the phase control more important so we’ll explain how to make accurate phase shift and phase delay tests.
An Overview of RF Evaluation Software Tools
Original Author: Min-Young Kim
This presentation introduces various third-party free RF software tools, which are useful for studying and evaluating basic RF concepts that lead to an actual RF design project. RF evaluation software tooling is not only useful for new RF applications development but can also help solve the mysterious real-world issues with better theoretical explanations. This presentation will discuss application examples with step-by-step tutorials, including the basics of impedance matching, RF circuit simulation, beamforming and TDR concepts utilizing free software, including SimSmith, Qucs, MATLAB (Octave), and LTspice.

Power and Module

High Speed Cres Testing: Loop and Group Cres Test Techniques
Original Author: Andrew Westall
Cres testing guarantees good device contact for high current pins in Smart Power Stage applications. Experience shows good contact is critically important for robust production-worthy test solutions and depending on the methodology, Cres testing can be burdensomely slow. This presentation will discuss two technique improvements to achieve <5mS per test Cres testing with mOhm level accuracy, including loop Cres testing, which utilizes existing high current test setups and connects SPU sense lines on the PCB in such a way that two Cres tests are made simultaneously; and group Cres testing, which operates by utilizing multiple resources connected to the same high current DUT pads, allowing multiple resources to be connected in such a way to measure 4 Cres values in series in the same “group”.
Quick RDSon Testing Utilizing HC Trace Magnetic Coupling
Original Author: Andrew Westall
High current testing of 2-5mOhm FET RDSons require special attention to the magnetic field. Non-optimized layouts can lead to several hundreds of uV of magnetic interaction between the force and sense traces that can take milliseconds of time to settle. Since this settling happens while high current is being applied it can dramatically increase the heating on device contactor pins, reducing their lifetime. In this presentation, we’ll review our experience with reconfiguring a board with magnetic optimizations. We’ll compare the original layout of the magnetic field, where ther is almost no drop-off throughout the PCB area above and below the high current trace and the related sense lines are closely coupled to the force lines; and the optimized layout, where the FH and FL traces are stacked on top of each other and the sense lines follow a new, shorter path, resulting in the magnetic field and interaction being drastically reduced.
A Digital Controller Test Solution for ETS-800
Original Author: Jeff Du
Digital controllers integrated with traditional discrete drivers and MOSFET structures can complete a multi-phase VR solution with minimal external components. It can be used in many different applications, such as desktop cores and data centers. Digital controllers with 1000+ test items include high frequency items (20MHz), high voltage accuracy items (1~3mV) and high pin counts (45-60 pins). This presentation will introduce the advantages of the ETS-800 for testing digital products, specifically how achieving better performance for test time, DIB design and cost of test.
Design Considerations for Low Leakage Measurement
Original Author: Stefan Chen
Engineers may face a challenge when designing low current measuring circuitry for pin leakage and isolation resistance. In consumer electronics, low pin leakage can reduce power dissipation. In power modules such as 110VDC railway applications or 1200VDC PV (photovoltaic) applications, there could be direct physical and electrical damage without isolation, so it’s generally necessary to strengthen the isolation. Current is required to achieve this higher isolation resistance and lower leakage. This presentation will discuss design considerations for measurement, including a circuit concept for circuit design, component selection that avoids affecting the performance of your circuits, and PCB design techniques for a circuit’s performance.
Application Guidance of I2C Bus Communications on the ETS Platform
Original Author: Patrick Zhong
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces, and other similar peripherals devices. The original I2C bus had a maximum speed of 100 KHz and most common applications still use this speed. Later the maximum speed was increased to 400 kHz in fast mode. The ETS platform provides an up to 466KHz speed fast mode I2C bus for application expansion. An I2C bus has two signals, along with a power and shared ground connection, one primary and multiple secondaries. The I2C bus is quite stable when the two signals’ connections are short and there are only several secondary devices but it changes dramatically when the physical connections are longer, the number of secondary devices increases, and the communication speed is high. This situation is becoming more and more common as the complexity of application hardware increases. This presentation will discuss the principle of I2C bus communication and how to deal with longer cable connections, many secondary devices and the isolation application of I2C bus.
Test Time Reduction Using UPD64 High Speed Capture on the ETS-800
Original Author: Doug Pounds
Workhorse 16-bit capture instruments on the ETS family of testers have traditionally been the APU and the QMS, which can capture up to 200 KHz on the ETS-800. The APU and QMS instruments have a 50 KHz and 100 KHz capture BW respectively. The UPD64 on the ETS-800 has a 16-bit capture rate up to 330 KHz and typical selectable bandwidths of 215 KHz and 650 KHz. In addition to a higher capture rate and BW, the UPD64 capture is capable of remote high/low sensing at the DUT for more accurate measurements. These features, coupled with an accumulator mode for instant results averaging and whereat function for threshold searching, means the UPD64 capture is the new standard for making fast, accurate measurements. This presentation will discuss how to take advantage of the UPD64 accumulator and whereat modes to reduce test time and increase parallel test efficiency.
Introduction to a 16-Site GaN Wafer Sort Solution for ETS-88
Original Author: David Ding
With the rapid growth of the GaN market, customers need more efficient wafer sort test solutions. This presentation will introduce a 16-site wafer sort solution for the ETS-88 system, including TIB, PIB and 16 customizable relay modules, which allows users to define the test flow to meet specific test requirements. With the upgraded tester configuration, the solution can reach a 1000V/12A test specification and can cover most of the GaN test requirements for wafer sort. Additionally, we will discuss the high voltage protection circuitry in the solution to protect the instrument from damage when a shortage occurs to one or more sites during high voltage testing, which also helps improve parallel test efficiency.
Arc Suppression During Power Discrete Testing
Original Author: Dean Garrison
Testing power semiconductor devices at high voltages and/or high currents carries the risk of damaging devices or test equipment through arcing or overheating. Smaller chip sizes pose even bigger challenges for tests at the wafer level. Wafer test of power semiconductor poses some quite specific challenges with test currents of more than 100 Amps and test voltages exceeding 1 Kilovolt. Well-proven for “classical” devices fabricated in silicon technology, examples being rectifier diodes, IGBTs, and power MOSFETS, high voltage arc suppression technology provides spark-free probing for devices made in Si, SiC, and GaN technologies with their inherent capability for smaller chip sizes and risk of sparking during wafer test. This presentation will discuss a process for reducing arcing during wafer test, thereby reducing the cost of replacing the probe and the damage to the wafer. We will review why and how to detect and control this arcing during wafer probe testing, and the causes and how they may be resolved to ideally lower the cost of probe testing by increasing the time between probe changes due to arcing.
The Basics of the HV Probe Code Library
Original Author: Charles Esteves
The HV Probe solution is being developed to address the need for a flexible multi-site wafer sort solution with scalable current capability for discrete devices such as, but not limited to, MOSFETs. The HV Probe solution is comprised of a set of hardware modules and a code library to simplify programming the hardware and executing common discrete tests. This presentation, which complements another that introduces the HV Probe solution (Scalable Multi-site Discrete Wafer Test Solution), will focus on the basic functionality of the code library and how a user can set up an application program to integrate and use the library. One of the main objectives of the code library is to simplify writing common discrete tests via canned routines or functions. A few examples will be provided to show how this can be conveniently achieved. These canned routines save the test or product engineer time and effort to bring up a test program and enables them to focus on yield issues or improvements. Available routines will be enumerated and an explanation of the design of the library will also be covered to illustrate the advantage of such an approach.
A Scalable Multi-site Discrete Wafer Test Solution
Original Author: Neil Niu
Today the discrete devices market is growing rapidly driven by the demand for green energy and the upgrading of more electronic systems. The industry is working to increase production, such as 300mm fab investments worldwide. The Superset project is in the process of developing a flexible multi-site discrete wafer test solution on the ETS-88DUO test system with scalable current capability. It provides up to 2KV/200A test capabilities for Si-MOSFET, SiC-MOSFET, and IGBT products with both Common-Drain and Top-Drain wafer type options, meeting the discrete industry's need to reduce the time to market and the cost of test. This presentation will firstly overview the structure of the Superset design, including system configuration, prober interface board and the role of the customization board. Then the effort on the safety mechanism is demonstrated by illustrating the interlock design and the high voltage considerations in PCB design. The main portion of this presentation will cover the principles and the waveforms of the typical test functions for MOSFET testing, which involves specially designed modules for test efficiency and reliability improvement, such as Interleave-MUX, Quasi Current Source, Current Limiter, and Gate Driver. Finally, we'll provide an overview of a test program that gives a view into how the ease of use and maintenance is achieved in the program design.
High Current Pulsed DC Testing Up to 4 KA with the HCU2000
Original Author: Ed Mateyka
With the adoption of GaN and SiC technologies and higher power requirements for power modules there is a need for higher levels of pulsed DC current. Teradyne has introduced the HCU2000 instrument as part of the ETS-88TH system to address the requirement for pulsed DC currents up to 4KA. This presentation will discuss the HCU2000, including using the instrument in native mode and the preferred method of using the Safe Operating Area Manager (SOA Manager) software to optimize test time. The SOA Manager is software that is implemented via various APIs that are part of the programming of the HCU2000. A description of the use of the SOA manager when using multiple pulses in a single test application will be covered, along with a description and examples of the actual use of the APIs. We’ll discuss how to optimize test time by minimizing the movement of the instrument power rail when using multiple pulses of different values in a single test sequence. The SOA Manager allows the user to find the optimal settings that are a compromise between the power rail movement of the capacitor bank and heating of the output structure resulting in greater throughput.
GaN Power Transistor Test Solution and Dynamic RDSon Test
Original Author: Grace Zhang
Gallium Nitride (GaN) power transistors are widely used in power products due to the excellent electrical characteristics: high switching speed, high breakdown voltage and low on-resistance, which offer the benefit of a product with smaller size and higher power. Using the silicon substrates manufacturing process, the cost of GaN power transistors is much lower in mass production for higher power products versus silicon power MOSFET’s. However, as a new technology, there are still technical difficulties in GaN power transistor manufacturing. Effective testing in production to screen out the defects to ensure device quality is important. An example is the dynamic on-resistance effect. This presentation will introduce normally off GaN power transistors and the differences compared to traditional silicon power transistor parameters and tests. This includes dynamic on-resistance test requirements and challenges. Also covered will be the Teradyne ETS-88TM test solution showing dynamic on-resistance test plots under stress. The test results will show how the Teradyne ETS-88TM with standard floating source and a proprietary test circuit can not only complete the fast test of dynamic on-resistance, but can also meet mass production test and characteristic analysis of GaN power transistors.
HCU2000 Best Practices: How to Program for the Best Performance and TTR
Original Author: Hideaki Nakajima
The HCU2000 instrument can provide up to DC 2000A pulse current per channel. The SOA Manager is a tool integrated within a number of HCU2000 APIs that helps minimize test time or time between pulses when using the HCU2000. The SOA Manager assists in setting rail voltages to the optimal point for a given set of pulses to minimize test time, checks time between pulses, and checks for instantaneous violations of SOA and Droop. However, there are some conditions which will cause a test time impact even with the SOA Manager. Since vrail/current setting, positive/negative current direction and the test order of those item combinations will impact test, we will discuss the parameters to consider to minimize the impact on the test time, and how those parameters affect the voltage/current output with waveform data.
Different PDS Structures for Parsing Parameters on the ETS-88
Original Author: Yoyo Zhang
As we all know, one of the benefits of Automatic Test Equipment (ATE) is easy operation and a user-friendly interface. For many ETS-88 projects, our users are demanding it for its intelligence and convenience and have asked if they could rapidly change the test conditions of the test item without opening the source code. Based on these types of requests, we combined the PDS function of the existing Eagle Vision MST to make the datasheet become an important input in the project. The user can place almost all of the parameters in the datasheet and then use them in the Visual Studio environment bypassing the parameters. This presentation will introduce three different PDS parameter structures and usage methods, which bring together fixed multi-column, programmable small multi-column, and programmable single-column formats to help the user choose the best method for improving efficiency.
Next Generation Smart Power Unit: The SPU8112
Original Author: Dennis Keogh
The push for higher site count and lower test times is driving the need for higher-density, medium-power instruments with improved performance. Teradyne's SPU8112 doubles the SPU2112 instrument density from 4 to 8; increases max current; includes a higher resolution meter; has higher bandwidth, separate outputs for audio source, a programmable Kelvin detect threshold, and voltage and current spike detection. This presentation will discuss the features and benefits of the SPU8112 and how it is enabling mid-range power test solutions to test more devices at faster test times. 

System Level Test

Titan RF: a System Level Test Platform with Integrated LitePoint Technology
Original Author: John Toscano
Mobile devices have transceivers that send and receive radio frequencies (RF) and there are rules that limit the power of device transceivers at various frequencies. To maximize the strength of the device’s signal, the device manufacturer must establish the performance and tune the power output to be just under the specified maximum power allowed by the government requirements. A leading Original Equipment Manufacturer (OEM) for mobile application processors and devices came to Teradyne with the challenge of integrating RF testing capability into System Level Test (SLT) to provide a solution that could connect their devices to a Vector Signal Generator and Vector Signal Analyzer (VSG/VSA) to perform RF power level calibration for broadband signals. RF test capabilities were built into the Titan SLT tester, with the goal being massively parallel, automated, asynchronous test of devices that require RF connectivity to ensure optimized performance of the device under test. The solution supports up to 320 sites of RF connected devices, and in cases where the devices require multiple antennas to be connected, Teradyne has developed miniature wide band signal splitters to connect up to 12 antennas per device, with the capability for 16 antennas in the future. This presentation will provide an overview of the solution and the benefits that can be expected including improved time to market, lower cost of test, highest overall equipment effectiveness (OEE), and online on-the-fly test instrument calibration.
The Advantages of Mechanical Standards for System Level Test Board Development
Original Author: Michael McKenna
Standard mechanical requirements for System Level Test Boards (SLTBs) can accelerate our SLT customers’ hardware development process, which is repeated with each new DUT type. The SLTB development process typically includes integration across multiple, third-party companies to create the unique PCBAs and IC sockets while still interfacing with Teradyne SLT test equipment. This presentation will describe the requirements and why they matter. It will also reference a recent Teradyne internal project that tested this very process on a commercially available DUT. The project included development of a Teradyne-made SLTB PCBA, and contract work for the unique IC socket and support mechanics for use on a Halos SLT tester. The SLTB IC socket development process was indicated with Yamaichi using the standard mechanical requirement for SLTB, and developed in-house by Teradyne’s Device Interface Solutions team. The success of this project and creation of standard SLTB requirements demonstrates Teradyne’s commitment to pioneering SLT test development.
Saturn HD In-System Slot Verification
Original Author: Yuthawan Srisook
In Teradyne’s Saturn HD tester there are 1080 slots/rack for HDD testing, with 12-18 racks per machine. During testing, slots fail and go offline, at which point the condition of the slot must be verified. In the past, this required removing the offline slots so diagnostic tests can be run on the bench, where there is a production test drive (PTD). The bad slots are sent for repair while the good slots are kept as spare parts. This process was both time and resource intensive. To improve this process, Teradyne has developed the In-System Verify (ISV) solution whereby instead of moving a slot from the tester to the PTD drive on the bench, we instead move the PTD drive to the slot inside the tester. This allows us to avoid removing the slot which may still be in good condition (even offline). This presentation will discuss the ISV solution, and its unique features that allow us to load the PTD drive to the input stacker of a production machine while the machine is running, without the need to stop the machine. The software handles moving the PTD drives to the target slots by automation and then sends the command to start testing. Once the test has finished, the automation will move the PTD drive to the next slots automatically. With this implementation, the number of slots removed from the machine is significantly reduced, and the number of verified slots per day increased significantly with fewer people due to process automation.
Calibrating Halos Pick/Place Functionality for Accuracy
Original Author: Jianfa Pei
Halos is a new system-level tester under development, with an automation sub-system that is a gantry style robot. The gantry beam has four sets of pick/place units running along its linear track. Each pick/place unit itself is a Cartesian style robot with its own X-, Y-, Z-, and R-axes. Therefore, a row of four devices under test (DUT) can be picked or placed simultaneously. This presentation discusses a series of accuracy related challenges and demonstrates how to calibrate the system to achieve required placement accuracy. The system relies on vision as its sensor of choice, with cameras mounted on the pickers, facing down, measuring the pick/place sites, and cameras mounted below the pickers, facing up, measuring the DUT offsets while holding the nozzle vacuum. The solution starts with calibrating the cameras, then proceeds to a number accuracy related challenges that will be detailed in the presentation. Only then can hand-eye coordination be achieved: namely the picker nozzle can accurately reach the camera-measured placement site. This presentation describes how we model the sources of inaccuracy and the techniques to calibrate them out.
Asynchronous Parallel Test with SLT
Original Author: Raj Tripathee
The phenomenon of semiconductor scaling, Moore’s Law, has increased the device density per unit area while delivering higher performance, low power consumption and low-cost devices, creating an even more complex system. Production testing of these systems to ensure overall system performance, quality and reliability becomes a difficult problem. System level test (SLT) fills the gap where traditional structural and functional testing falls short and has become an important test insertion in the semiconductor test flow. This presentation will discuss the trend of this fault coverage with a semiconductor test system, which functions as multiple logic testers where each logic tester operates independently and asynchronously from the other despite the complexities and additional test cost. We will also discuss a test system which can conduct asynchronous parallel testing on multiple devices and explore how asynchronous parallel test makes SLT a lower-cost insertion and high-volume manufacturing (HVM) production-worthy. In addition, massively parallel asynchronous test data and upstream data analytics can enable adaptive test decisions to be made between wafer, functional and system level test further reducing the overall cost of test.
An Overview of System Level Test
Original Author: Peter Reichert
As semiconductor geometries become smaller and greater complexity is pushed into ICs and packages, it is increasingly difficult to maintain high fault coverage. The traditional combination of automated test program generation (ATPG) and scan has enabled very high fault coverage but an increasing portion of complex circuits are moving out of reach of these techniques. Further, testing in "test modes" can mask faults that are only expressed when the part is operating in its functional mode. System Level Test (SLT) is a test technique that addresses these challenges, a functional test where the DUT runs as it would in its end application, including interfacing with real hardware peripherals and running real software. By running the DUT as it would in its end application we can test the interfaces between IP blocks without writing challenging test vectors; test the interactions between IP blocks; test HW/SW interactions; and run for a longer time to help reveal intermittent faults. This presentation will discuss what SLT is, and how it can improve final product quality and reduce time to market.
High Protocol Scan with System Level Test
Original Author: John Jackson
Test challenges continue to increase as semiconductor geometries become smaller and packaging complexity increases. System level test (SLT) is becoming more common as a method to meet these challenges. In parallel with the rise of SLT, testing across the lifecycle of parts is also becoming more common. With these changes, it is increasingly useful to run scan tests at SLT and in the field. Running scan at SLT is a low-cost way to run high-yield patterns that might seem marginally cost effective to run at final test. Running scan in the field provides better diagnostic capabilities and high-protocol scan testing – serial scan using high level protocols such as USB or PCIe – is a way to achieve these goals. The use of standard protocols allows the DUT’s scan features to be easily accessible at SLT and in the field given the necessary hardware can be designed to be highly parallel (SLT) or portable (field). This presentation will discuss what high-protocol scan testing is and how it meets the challenges described above.
Inline Slot Recovery for Titan
Original Author: Tae-Won Kim
Teradyne’s Titan SLT system is constantly improving and the scan test system is the most mature. Composed of one appliance PC and 2 slots, each of these communicates continuously and problems in either system impact the other, causing the slot offline rate to increase. A high slot offline rate results in low slot availability in a system, which negatively affects productivity. It was discovered that some specific slot offline reasons on scan test systems could be recovered by initializing the appliance PCs and rebooting slots but one Titan SLT system can have 54 appliance PCs and 106 slots. In a production line, several thousand appliance PCs and slots are running, requiring many resources to physically check and initialize appliance PCs and slots, which must be done carefully while the tester is running. This presentation will discuss the Slot Offline Helper, a solution developed to recover appliance PCs and slots via reboot while the tester is running. A tool monitors the test result per device and if it detects specific failures related to recoverable slot offline reasons, the tool will attempt to reboot the appliance PCs and slots before failing them to a slot offline state. With this tool, the slot offline rate and slot availability improves on scan test systems.

Software and Tools

PyGXL: Hints, Tips, and Best Practices
Original Author: Lawrence Luce
PyGXL is a bridge between Teradyne's IG-XL test programming environment and the popular Python programming language. Teradyne introduced PyGXL in 2021, and several customer teams are now using it to streamline new product introductions at the ATE test stage by allowing them to leverage the Python programs written by Validation Engineering teams to more quickly bring up device tests on the Teradyne platform. This presentation will discuss best practices to smooth the transition between bench testing and ATE, including a Python program architecture that encapsulates the bench equipment hardware interface commands into one (or a few) file(s) with dedicated classes. This facilitates simply replacing them at ATE test with the equivalent interface classes that instead call IG-XL instruments. We will also detail a Python utility to print and datalog from Python to: (a) the immediate window (with bold and color for debug); (b) the test output window; or (c) the datalog. Another example shows how to setup an IG-XL breakpoint function that can be called from Python breakpoints, which allows users to stop the program flow from IG-XL without crashing the test program. PyGXL, and these hints and utilities, makes achieving bin 1 faster and easier.
Test Development Nirvana: Utilizing Design Files with PortBridge
Original Author: Richard Fanning
Teradyne’s PortBridge software provides widespread support for Serial Vector Format (SVF) files that customers have found very useful, however the one downside of this file format is it's limited to JTAG. Most devices have a JTAG port but it’s also common to have other protocols like SPI, I2C or a proprietary format, and we have received requests from the field to provide the same SVF VBT interface, file support and debug tools for these other protocols. This presentation will discuss Portbridge’s new Test File solution, an XML-based format that can be used to teach PortBridge how to parse and execute files. Once loaded, PortBridge optimizes execution time, provides robust result retrieval interfaces and is a full feature debug tool. This suite of features helps the test engineer quickly take files from DFT/design and move them directly into a test program with no conversion steps needed, speeding up test program development while also improving feedback and communication with the design team when debug issues arise.
Code is Code and an IDE is Just a Fancy Text Editor, Right? Not Quite …
Original Author: rAiner Gruber
Starting with IG-XL version 10.40, the new feature, .NET Development in IG-XL, will support the ability to alternatively write test methods in the VisualBasic.NET language. The Microsoft .NET environment consists of a rich and powerful programming ecosystem and utilizes the Microsoft VisualStudio IDE for highly efficient code development. Flexible concepts for code modularity, reuse, refactoring and maintenance – well-recognized throughout the software industry – can now efficiently be applied to create and maintain IG-XL based test programs. This presentation highlights some of the most fascinating features and demonstrate how they are used. With examples selected to have a strong ATE relevance, the audience will learn how to apply these techniques to their workflows for better code quality and more efficient project execution.
The Impact of IG-Sim on Efficient Program Development
Original Author: Kitty Belling
Device test programs are highly modular and often share code and patterns with other devices within a family. Common blocks within these device families can be reused and do not need to be re-developed. Development time is greatly shortened if device data is reused as well. If test engineers can recycle both code and data from one device test program to another, entire blocks of tests can be transferred and simulated offline in a matter of minutes. IG-Sim in the Oasis toolset adds this functionality to IG-XL. Within IG-Sim, engineers can store information from the tester in an offline database, which adds device data to test programs. This prevents test engineers from repeating development and debug, as entire databases can be transferred to simulate new silicon with existing data. Program developers can use previous device records to perform regression testing with ease. Projects with limited tester availability benefit by having data available offline. This presentation will discuss how IG-Sim is a key addition to the device workflow for reduced time to market.
MIPI I3C: an Introduction to Testing the Evolution of the I2C Bus Standard
Original Author: John Rowe
The MIPI I3C bus interface specification used in connecting peripherals to application processors for mobile, IoT and automotive applications is an evolution of the I2C bus specification. It features backward compatibility with I2C while offering improved throughput as well as features like in-band interrupts, which allow for higher performance sensor interfacing. This presentation will begin with an introduction of the I3C standard protocol, including the similarities and differences with respect to the I2C standard. We will then discuss some of the issues and challenges that arise in testing the I3C interface and the recommended approaches. Users will learn how the UltraFLEX Protocol Aware capabilities can be used to successfully implement tests utilizing the I3C bus. Taking debug one step further, we will introduce users to the critical role that PortBridge can play in ensuring engineers can debug quickly and efficiently at the protocol level and significantly reduce time to market.
Plot Tool Deep Dive
Original Author: Ralf Baumann
The Plot Tool was introduced in IG-XL 10.10, replacing the previous WaveScope tool, and comes with a completely new and modern GUI to help better visualize and analyze captured data. This presentation will provide an introduction to the tool and its different features to explain how it can be used to help with the daily debug and analysis of collected data. It will also review the latest features introduced in the new IG-XL version, including the ability to display sourced waveforms or captured DspWaves, scale waveforms, and perform trace analysis and waveform calculations using the Trace Calculator.
Git Your Test Program Under Control
Original Author: Dan Thornton
Git is, by far, the predominant revision control system used in the software industry. SVN is the predominant revision control system used by Teradyne and many of our customers, however the time has come to switch to Git due to a confluence of factors including increasing demands for DevOps workflows in test, the upcoming release of the .NET development in IG-XL, the built-in revision control integration in Visual Studio, and the availability of GitHub Enterprise. This presentation will briefly introduce Git, highlight the differences between Git and SVN, and explain the concept of distributed repos. We’ll also discuss the issue of pattern files in the repo and describe how Git LFS (Large File Storage) solves this issue. The presentation will walk through the workflow for two scenarios, including a simple one-person-show using revision control for a fairly simple test program; and a team collaborating on a large program with (imperfect) modularity and many changes. While Git and SVN solve the same problems, the workflows described will demonstrate the significant advantages Git has.
Deep Data Analytics Advances Device Testing with Machine Learning
Original Author: Marc Hutner & Rich Fanning
Realizing the next level of device quality and understanding in test engineering requires new solutions beyond the standard statistical data techniques. This involves looking beyond single test statistics to system-level coverage techniques, while ensuring minimum production risk. By combining on-chip agents with advanced analytics and machine learning in the cloud and at the edge, end-product performance, reliability and quality improvements can be achieved. The benefits of this approach go beyond semiconductor testing, extending to system level test and in-field monitoring. This presentation discusses the underlying technology provided by proteanTecs and how it can be combined with UltraFLEX and UltraFLEXplus workflows to improve the ability to ramp devices quickly without additional product development risk to deliver a higher quality product.
A Solution for 93K to UltraFLEXplus Program Conversion
Original Author: Chao Zhou
As the number of conversion projects grows, converting 93K (7.X) to UltraFLEXplus programs efficiently is a common issue faced in the offline coding stage, including ensuring the test conditions and parameter of the output UltraFLEXplus program is consistent with the original program. This presentation will detail how to simplify the conversion steps and improve conversion efficiency, including a toolkit for 93K ASCII file conversion, including flow, AC/DC specification, pin level and pattern set, and a method to convert X1 mode BINL vector to ATP patterns and timeset (basic) sheet. We’ll also review a mapping table of 93K test items to UltraFLEXplus test items to ensure the quality of the conversion. This table contains the test conditions, the vectors used, and the test parameters for each test item in the project, which can be used to manage the quality of the converted program.
MST Test Program Skeleton Generator: A Shortcut for Test Program Development
Original Author: Marcus Shu
Creating new test programs can be a time-consuming task especially when implementing coding best practices and including user libraries, which may impact a project’s time-to-market and overall quality. The Test Program (TP) Skeleton Generator provides a method for automating the creation of test programs for all EV-MST test platforms. With the help of the TP Skeleton Generator and its provided default test program templates, developers can elegantly complete the first step of test program development by completing one file (i.e., LimitSheet.xls) and largely avoid repetitive work, including test program structure building (i.e., product datasheet (PDS) files, test program files), reusable code writing, and common and custom libraries linking. In addition to the default templates, the full power of the TP Skeleton Generator can be realized by creating and using customized test program templates, which can include customer-specific libraries and coding standards. This presentation details the power, scalability, and flexibility of this tool with a special focus on the new enhancements introduced in version 4.0.
Site-Aware DIB Identification
Original Author: Jozef Molnar
In a test environment, logical test sites (of the test program) are associated with hardware test sites (of tester resources and sockets/probes). In general, accidental exchange of test sites can lead to yield loss, or worse, release of failing devices. It is therefore important to carefully ensure correct site assignment in environments with flexible hardware, like cable interfaces to rotary handlers with multi-station test programs. Regardless of the test methodology (index-parallel or multi-site) we must ensure that each software site talks to its dedicated test board. There should be mechanical keys installed on the handler to avoid the exchange of hardware units but there could also be electrical identification of those units to increase the level of security. This presentation will describe a method that ensures correct site identification from the software to the interface boards for a soft-docked rotary handler concept, either index-parallel or multi-site. We'll discuss the advantages for the program, including managing per-site (or PCB specific) calibration values, hardware expansion and more.
Addressing Issues and Submitting Problem Cases
Original Author: Chuck Gaboriau
Teradyne is investing in systems and processes to speed the resolution of issues and central to that strategy is the knowledge base contained in eKnowledge. Users are strongly encouraged to use eKnowledge to resolve issues immediately, and if not, submit a case that will be investigated and resolved by an engineer. This discussion will focus on the process for finding solutions to problems, as well as how to submit a well-formed case for issues requiring further investigation.
The Emerging Challenges of HPC Scan and Functional Test
Original Author: Ken Lanier
Transistor counts and the number of IP cores for HPC devices continue to climb with new process nodes. Traditional GPIO-based scan strategies are becoming a limitation because they do not have enough data bandwidth. EDA suppliers are providing new solutions such as packetized scan data and scan over SERDES interfaces. There are also new EDA tools to perform functional test on ATE over the SERDES interface. This presentation will review these new EDA trends and how they impact test program generation and device bring-up. We will also discuss which of these new tools are likely to find wide adoption and why.

Production Integration

UltraFLEXplus Test Cell Solutions for Chip Probing, Final Test and Failure Analysis
Original Author: Daniel Park
Due to the global pandemic, billions of integrated circuits (ICs) will be needed to not only interconnect and control machines, objects and devices but also deliver multi-Gbps peak rates, ultra-low latency, massive capacity and a more uniform user experience. We are seeing demand for higher quality levels of test cell solutions (TCS) and faster time to volume production as products become more complex, and choosing the right test cell solution for mass production is a critical factor in meeting the requirements for chip probing (CP), final test (FT) and failure analysis (FA) environments. This presentation addresses best practices to ensure quality of test for mass production solutions, introducing industry-proven test cell solutions for the UltraFLEXplus family in chip probing, final test and failure analysis. To address quality of test issues, we will discuss pin count and force trends in real-world applications vs. test site increment, and provide options for UltraFLEXplus test cell solutions and DIB/PC center stiffener and/or backer.
An Introduction to Teradyne’s DIB Diagnostic Tools
Original Author: Dany Wang
DIB complexity doubles every four years with total hardware cost increasing rapidly, and a solution to quickly and efficiently verify DIB quality is imperative. The goal of DIB DIAG products is to identify DIB-related failures at both the NPI phase and the production phase, and help DIB DIAG application engineers quickly develop DIB DIAG test programs to perform quick troubleshooting in different phases. Early detection of DIB-related issues will improve time-to-market and decrease costs. This presentation will discuss Teradyne’s DIB DIAG products for different tester platforms, including UltraFLEX, UltraFLEXplus, J750, ETS364, and the ETS800. We will detail their general structure; current state; how they have evolved, becoming more intelligent, with increased test coverage and less manual work; and the application process and strategy.
Tips and Tricks for Improving the Quality of Software
Original Author: Christine Soh and Laurent Bonneval
In the world of software, solutions are getting more and more complex, including test programs and production software. The rudimentary practice of testing software with black box testing methods, such as error guessing in the production environment, may have worked in the past but the future looks different, especially with highly complex software. Writing software that is expected to run incessantly introduces new issues that need to be considered, including will the new modifications introduced change the behavior of the current software; did we test everything; and how do we implement tests efficiently? With the pressure to reduce development time, it is not uncommon for parts of the software to be outsourced to different teams, only to be integrated in a later stage of a project. Because of this it is essential that a modification done by one development team does not affect the work of another. This presentation will discuss the concepts of unit tests, integration tests, and test coverage and best practices for overcoming the obstacles to deliver high quality software.
Probe Cards and DIBs in the Era of Complexity: A Fresh Look at Total Cost of Ownership
Original Author: Steve Ledford
As test complexity grows, indications are that the cost of consumables (probe cards and DIBs) is increasing faster than other major categories of ATE and material handling. It has been more than ten years since there was an in-depth analysis of the factors driving these costs. In that time the technology for interface, probe needles, and mechanical integration has changed significantly and the “rules of thumb” on how to manage interface hardware need to be updated. This presentation will discuss an updated cost of ownership model and take a fresh look at the cost drivers that dominate consumable spend today, including an outlook for the next 8-10 years. We'll also discuss the solutions that Teradyne has developed to achieve the lowest cost of ownership.
Hardware Complexity Review & Challenges
Original Author: Eric Shoemaker
As the need for higher speed, density, and power drives IC design roadmaps, interface hardware designs continue to become more complex and more challenging to deliver. Teradyne’s Device Interface Solutions (DIS) organization has created an integrated development process to deliver the highest-performing, most complex hardware designs on-time for our customers and their test partners. DIS’s focus is on minimizing the pain and costs caused by hardware bring-up failures at customer test sites and preventing wasted time during critical silicon and test program debug activities, ultimately allowing customers to improve new silicon time to market and to be confident in their ability to ramp to volume production when needed. This session will focus on the complexity of hardware design and solutions for solving these challenges.

Low Cost Consumer

Audio Test Solutions for ETS-800
Original Author: Michael Davis
High resolution audio recording and playback formats have been available to the professional and individual user for years. Consumers are able to create and listen to digital audio captured well in excess of the traditional “CD-Quality” 44KHz, 16-bit standard released back in 1982. While debate continues as to the audibility of the additional information these systems capture, these formats are caught up in a relatively new spec-war that is driving the need to test beyond the traditional limits of 96dB at 44kHz. This presentation will explore the performance of the native instruments in the ETS-800 for these higher levels, as well as describe techniques at the DIB and software level to extend the performance of these instruments. Techniques to be explored include bandpass filtering the source waveform, notch filtering and gain to measure low amplitude harmonics, and using the built in gain of the SPU-8112 to measure lower noise floor.
Efficiency Comparison for Testing a Large Number of DC Items for FPGA Devices on Different IG-XL Platforms
Original Author: Rainbow Shen
There are a number of DC test items when testing FPGA devices, especially for high pin count devices. Different IG-XL platforms have different DC test efficiencies, whereas functional test efficiency is almost the same. Given that we can easily calculate the optimal site count based on the configuration of each platform, DC test efficiency is key to determining which platform provides the best cost of test for FPGA devices. In addition to the DC item test efficiency, it is also important to know the proportion of the total test time represented by the DC test items. This presentation will compare FPGA DC test efficiency for the J750HD, UltraFLEX and UltraFLEXplus. We’ll compare and analyze the test time and PTE based on DC instrument measuring time and highlight the results on each platform. The results will be presented for different situations, including different device pin counts, site counts and measuring times. This data will serve as a reference when choosing the IG-XL platform that best meets the cost of test requirements for testing FPGA devices.

Virtual Live Session

Teradyne Roadmap Presentation
Original Author: Trent Weaver
Come hear from Teradyne and industry analysts about how trends in the automotive market are impacting semiconductor test, and what it means for the rest of the industry. Learn how Teradyne is addressing these challenges with new features and roadmap items across ATE and System Level Test platforms.
Advanced SOC Techniques | Virtual Live Panel Session
Big Digital Device Challenges | Virtual Live Panel Session
Software and Tools | Virtual Live Panel Session
Automotive Test | Virtual Live Panel Session
ETS-800 Advanced Techniques | Virtual Live Panel Session
Power Discrete Test | Virtual Live Panel Session
RF/mmWave Techniques | Virtual Live Panel Session
RF/mmWave Advanced Usage | Virtual Live Panel Session
System Level Test | Virtual Live Panel Session

TUGx Resources

Through TUGx, we strive to deliver local access to our technical personnel, sharing knowledge and making you an expert, as you gain a deeper understanding of our products and services. The content presented at the seminars is intended to help you get the most out of your Teradyne test equipment.