UltraFLEXplus DCVS Alarm Setting to Avoid Burned Probe Cards
During wafer probe testing there was a situation in which a probe card burned twice in two weeks. We determined that the root cause was the high current functional tests. To resolve the issue we collected current profiles for all functional items so that the designer could analyze and provide updated device settings for some of the high current test items. In addition, we also adjusted the programmed settings of the UVS64 to reduce the duration of any over current events. This presentation we will review the DCVS programming features which can be used to reduce the likelihood of a burned probe card, including VSlewRate in Pin Levels sheet, DCVS Behavior, Fold, and Timeout Settings and power off sequencing.
Understanding UltraFLEXplus Specifications
Teradyne tester specifications list instrument capabilities and limitations, and the accuracy of instrument parameters. Words like guaranteed, typical, and measured are defined by the specifications, and manufacturing each instrument includes measuring the values noted in the specifications. Using the UltraFLEXplus as an example, this presentation will address what is specified, and what is not, and review the specified calibration process to ensure specified parameters continue to be accurate, enabling the user to design accurate testing and guide them to appropriate guard banding.
Efficient Jitter Measurements of Low Frequency Asynchronous Clock Outputs on the UltraFLEX Family
Devices with interfaces like Ethernet (RMII) that also work with 10/100 Mbps speed require a relatively low 25/50MHz clock output. The clock, in most cases, is generated either from an external crystal, or an internal or external clock generator that runs asynchronously to the tester clock. Besides measuring the frequency of those output clocks, it is also necessary to measure the Random Jitter (RMS Rj). The UltraFLEX family offers a fast Walking Strobe measurement capability on the UP1600 and UP2200 to measure the random jitter (Rj) as well as data dependent jitter (DDJ) of output signal edges. Unfortunately, a clock period that is a few picoseconds faster or slower than the expected period, can cause the measurement to fail, especially when many sites need to be tested in parallel, since each crystal has a slightly different frequency. This presentation will demonstrate some limitations when measuring Rj jitter on low frequency clocks using the Walking Strobe method. It will provide possible methods on how to test sites in parallel with an efficient test time using different setups and methods. Finally, it will compare the different methods in terms of accuracy and test time.
112Gbps PAM4 and NRZ PHY Layer Testing Using Third Party Instruments
Network processors, infrastructure networking, and backbone IT data farms are leading the charge in applying FEC encoding and active equalization to PAM and NRZ SERDES channels to achieve the next round of step function improvements for data rates at 56Gbps, 112Gbps and even >200Gbps over single channel copper. Automotive, imaging, and consumer are not far behind. With this new technology, the industry is demanding ATE-based test capability. This presentation will discuss the results of a “level 0” integration of third-party hardware, software and signal delivery to provide lab quality near DUT source and measurement capability. The solution described will include BERT drive and receive up to 56Gbaud, and an exciting oscilloscope-like capability through a high performance DSO from Multilane. The challenges overcome will be described and the real performance capability achieved will be demonstrated. The presentation will also discuss the tradeoffs between performance PHY testing and “low protocol” functional test, along with a strategy for transitioning between the two testing types discussed.
Alarms Reporting, Processing and Debugging on UltraFLEXplus
Alarms are a key component of Teradyne’s test systems. They indicate a hardware condition caused by a bad device, an incorrectly programmed instrument, or a test system failure that may invalidate a measurement, potentially causing a bad device to be sorted as a bin1. The UltraFLEX tester family has implemented a fully-integrated Alarm Service that ensures hardware alarm conditions are monitored, filtered, reported and processed properly without requiring additional user code to the test program. The user can then choose to have the device binned either to the fail bin associated with the alarming test or to a dedicated alarm bin. The UltraFLEXplus and its PACE pipeline architecture introduced nuances in the way alarms are handled. This presentation will describe how the alarms reporting and processing work, present different debugging tools and review best programming practices.
Implementing and Debugging the Serial Wire Debug Interface
Serial Wire Debug (SWD) is a 2-pin electrical alternative JTAG interface that uses the same JTAG protocol on top. SWD uses an ARM CPU standard bi-directional wire protocol, defined in the ARM Debug interface V5, enabling the debugger to become another AMBA bus master with access to system memory and peripheral or debug registers. SWD uses fewer pins than JTAG, but has a higher transfer rate and is more stable. It is a useful interface for ARM devices or IP core testing and is gaining acceptance as the preferred interface for firmware burning. This presentation will introduce the SWD interface protocol, describe how to implement it by pattern and offer tips for online debugging.
Introducing Repeatable Code Sequences on the UltraFLEXplus
A common requirement of ATE device test solutions is to provide tight timing repeatability across a sequence of tester actions. This capability is needed to meet device specs, optimize test time or maximize yield. The usage varies widely across device types and test blocks within a program, and often spans analog and digital tester resources. The Parallel Advanced Command Execution (PACE) architecture, unique to the UltraFLEXplus, provides an exclusive approach to a repeatable test sequence while being extremely easy to implement. With only two lines of additional code, a section of tester commands can be set as a “Repeatable Code Sequence” block. Another important benefit is that the development and production environments all use the same implementation and behavior, facilitating debug and correlation by not introducing different modes, which is not possible with solutions that develop and debug in a code approach but convert to a pattern-based approach for production. In this presentation, you will learn about this new capability, available in IG-XL 10.30.00, which can work seamlessly with the PACE architecture to preserve the test time optimization already provided by the system.
Fast Throughput on the UltraFLEXplus Enabled by the PACE Architecture and Site-Aware Variables
The introduction of the UltraFLEXplus has shifted the paradigm of testers to enable faster communication and throughput via the Parallel Advanced Command Execution (PACE) architecture. However, even experienced users assume this new architecture is an extension of the legacy “data backgrounding” capability of the UltraFLEX and DSP PCs, however it’s not. The controller PC workstation works in concert with enterprise network processors onboard the instrumentation to pipeline tester interaction into multiple, distinct communication channels. Command, results, alarms, datalogging, and DSP processing all execute from their own threads. Unlocking this potential throughput improvement does not requires highly complex code practices. Using native site-aware variables that are part of the VBT code base, IG-XL takes advantage of the parallel computing and communication environment while retaining a simple programming model to ensure fast multi-site test program bring-up. In this presentation the conjunction of easy coding and fast performance will be demonstrated, along with examples of improving code to eliminate differences between single site and multi-site programming.
Understanding the Test Challenges of SCAN Using 1149.10 and How UltraPin2200 Solves Them
Scan has always been a key test item for SoC devices. With the ever-increasing number of gates, the test time for scan continues to increase. Customers face tough decisions weighing test time versus coverage. Increasing the scan bandwidth can be used to counter the ever-growing scan requirements but before considering how to increase this, customers must also consider other complexities. Complex hierarchies create challenges to implement the DFT required for scan. Additionally, the constraints on the number of pins available compounds the complexities, all of which points to a need to find new approaches to reduce the complexity and counter test time. One approach stems from IEEE 1149.10 specifications, in which Siemens has developed a solution using their Streaming Scan Network to achieve scan over SerDes. This presentation will explore the implementation Siemens has created for IEEE 1149.10, the test challenges and how UltraPin2200’s unique architecture solves them.
Using a DUT’s HSIO Interfaces in a Fully-Functional Protocol Configuration for SCAN Test
Advanced Digital Devices are experiencing exponentially increasing test challenges from multiple directions. The industry is responding by introducing new approaches to test that expect to disrupt the status quo. One key area of opportunity is in scan and structural test, with a number of emerging options that will improve efficiency and effectiveness. With more transistors to test and new failure modes due to advanced technologies, the amount of total test data volume continues to grow at an exponential pace. The existing standard approaches to DFT structural testing, such as scan, have encountered practical limits, in part due to data bandwidth from limited GPIO rates and limited or fewer pins available for scan. One of the new leading options to overcome these limitations is to utilize existing High-Speed I/O interfaces, which promises to provide much higher test data bandwidth while also reducing the number of digital test pins required. In addition, it offers exciting new opportunities such as leveraging the ability to perform DFT test across the silicon lifecycle, from ATE through System Level Test (SLT), and even through to the final in-field environment. This presentation will explore the benefits and test considerations of using HSIO interfaces in their fully-functional protocol configuration for structural test. It will describe Teradyne's strong development partnership with Synopsys for their DesignWare HSAT and Test MAX ALE products, and how we are enabling the most advanced test solutions for the future of protocol-based test.
Device cooling is receiving renewed interest as large digital devices become more commonplace in applications such as Artificial Intelligence (AI), Machine Learning (ML), and non-battery based applications. We’ve seen processor technology evolve over the years from air cooling to liquid-based cooling to device-responsive cooling, however some of the objectives of cooling remain elusive due to the proximity of thermal sensing, cooling techniques, and device packaging. This presentation will discuss the objectives of device cooling, specifically, avoiding front-end hardware damage and yield improvement, as well as some of the obstacles to maintaining a constant temperature at the transistor junction (thermal mass, time constants, effect of different cooling media). Additionally, the Automatic Thermal Control (ATC) cable option for the UltraFLEXplus will be reviewed to demonstrate its capabilities, and how to use this interface to communicate with external thermal equipment.
Saving Vector Memory on the UP2200 with Functional Vector Compression
Digital devices continue to grow the need for vector memory. While scan patterns often consume the bulk of the vector memory used by a test program, functional patterns can still comprise a significant portion of overall vector memory. Teradyne’s UltraFLEXPlus UltraPin2200 and UltraPin2200+ enables memory sharing across 16 channels, and to further aid in making the best use of the instrument’s vector memory, IG-XL 10.30.10 is adding three new features that can reduce the size of a functional pattern. These features include two new pin setups, allowing the declaration of pins as input or output only through a pattern, which reduces usable states for pins while saving memory. Alongside these pin setups are two features to aid in implementing SCAN memory savings into parallel patterns easier, including a new syntax that aligns SCAN blocks to parallel vectors, and flexible scan, which allows the use of a subset of defined SCAN pins in each SCAN block. This presentation will give an overview of these new features, outlining how to use them, when they are most useful, and their limitations.
Improving Multi-site Efficiency with Independent Patterns per Site
Test solutions use many different techniques for improving throughput, reducing test time, and ultimately lowering the cost of test. The most fundamental of these techniques is to test multiple devices in parallel but as adaptive test methods seek to optimize the yields of increasingly complex devices, the throughput benefits of multi-site testing may be reduced. Different devices may not only require unique power or timing settings but may also need to execute different sets of pattern vectors. This last requirement has historically required that sites run serially, resulting in increased multi-site test overhead. This presentation will demonstrate how to leverage the hardware and software features of the UltraFLEXplus tester to improve multi-site test efficiency by running different patterns simultaneously on different devices. The key enablers of this capability are the highly flexible architecture of the UltraPin2200’s independent pattern generators, as well as new software features that present simplified programming models for executing different patterns per site. The presentation will also explore extended capabilities, such as CPU loops and instrument operations.
MPD Bus/Interface Characterization With or Without Source-Synchronous Hardware on UltraFLEX
For a custom Parallel Data (MPD) bus/interface, the differential clock output from the DUT and the 28bit parallel data output pins from the DUT at 1000Mbps have a source-synchronous relationship. Classical functional testing methodologies do not account for such characteristics and as a result, if the standard test comparators on fixed edge in the vector is used the output data may fail the requirement. Source synchronous testing provides an effective method for eliminating phase and voltage jitter by using both clock and data signals from a DUT. This presentation will describe the precondition of source synchronous uses and DIB design, UltraPin1600 channel selection guidelines and the test requirements of MPD for this case. We’ll also compare the standard functional test with a workaround method of using customized multiple time sets of strobes, with source-synchronous to collect clock reference offset and output data voh/vol parameter for capturing and post-processing to check the shmoo eye. Finally, we’ll compare and contrast the stability and efficiency with and without source-synchronous.
Using TestInsight to Convert High Speed Scan STIL to UltraFLEX/UltraFLEXplus Patterns
Advanced processes are driving rapid growth in testing with a need for new approaches to testing at higher speeds. High-speed scan testing for IEEE 1149.10 has provided one option. Serial scan testing requires a handshake between the high speed serial and JTAG ports, which has introduced challenges for traditional ATE test methods. Dual time domains for high-speed serial lanes and setup patterns are required to start both together or to execute one while the other one is in keepalive. In cooperation with the electronic design automation (EDA) vendor Siemens Mentor and the ATE Software vendor Test Insight, Teradyne has created a test solution for our tester platforms. This presentation will discuss the challenges of serial scan testing and review the TestInsight ATEGen software solution for IEEE 1149.10 pattern generation to convert Mentor STIL files to ASCII pattern files on the UltraFLEX and UltraFLEXplus testers.
Current Profiling: In a Class of Its Own
One of the most helpful debugging aids is a clear picture of what’s occurring at a given point of failure. In the case of power instruments, this clarity can come from a current profile of a failing or alarming power supply. A current profile shows the measured behavior of the loads on a device, which makes it an important tool for identifying major current draws and spikes. With this information, test engineers can correlate on-tester device performance with the designer's expectations. This is true both for a big-picture view of the entire program and for a closer look at a pattern. This presentation is a companion guide to a Visual Basic class module that serves as a tool for collecting current and voltage profiles. This tool can be used to create a profile using any DCVI or DCVS instrument, such as the UVI80 or the UVS256, and can be imported into IG-XL test programs, adding code wrappers around the code to be profile. The class then stitches the collected profiles together and outputs a single profile of all wrapped sections of the test program, as well as optional individual profiles. This presentation will demonstrate how to use the tool, as well as best practices and useful tips.
Pattern Compilation Multithreading
Large test programs can contain thousands of patterns and compiling ASCII patterns to the binary pattern file format using the Windows Pattern Compiler can takes hours if not days. The extensive time spent on compilation is often caused by two factors. First, the single-threaded nature of the pattern compiler, where patterns are processed one at a time, resulting in the underutilization of resources on computers with multiple cores. Second, the overhead introduced by waiting for the pattern compiler to start up before compilation and close out after compilation, resulting in a significant amount of overhead time spent for each pattern. Creating a code function or script to wrap around the Pattern Compiler Command Line Interface allows for flexibility in the usage of the tool, creating opportunities for significant improvements in the tool performance. This presentation will discuss best practices for wrapping a command line tool, multithreading the pattern compiler to process multiple files simultaneously, and how best to reduce overhead between compilations.
Tester Performance Challenges for WiFi7
WiFi7 and new cellular standards will create additional challenges for testers and test strategies. Testers will need to measure higher and higher levels of performance, while lowering cost of test through higher tester throughput. This presentation will discuss new architectures for RF instruments being deployed and how new DFT strategies are being employed to simplify test and reduce costs.