The PACE architecture introduced by UltraFLEX plus is widely known among engineers. This architecture introduces asynchronous instructions between the host PC and DMC, resulting in the pipeline stall or pipeline full speed (also known as pipeline backpressure) phenomena. Both of these phenomena exhibit analogous behavior in timelines data, characterized by large gaps in host. A significant challenge arises from the tendency of general users to confuse pipeline full speed with pipeline stall, often leading to wasted efforts in addressing perceived but non-existent pipeline stalls. This paper presents a method to help users better understand and differentiate between pipeline stall and full speed. Additionally, a quick method for distinguishing the large gaps caused by these two phenomena is introduced.