Innovations in semiconductor technology—such as advancements in AI high-performance computing (HPC), Angstrom-scale silicon process nodes, silicon photonics, and automotive xEV wideband gap power transistor applications —require automated test equipment (ATE) to evolve at an unprecedented rate. As chip complexity grows, the challenges in design, manufacturing, and test multiply. It is a complex landscape, with profound implications for the ATE sector, crucial in ensuring that today’s increasingly advanced chips meet the highest standards of quality, reliability, and performance.
With this in mind, read on as Teradyne’s Dr. Jeorge Hurtarte discusses the trends shaping the future of the ATE industry, and how innovations in test methodologies are adapting to meet these challenges.
A new era of semiconductors: meeting demand across sectors
The semiconductor industry is expected to reach one trillion dollars in revenue by 2030, driven by high-demand areas like AI HPC and silicon photonics in data centers, edge AI applications in smartphones, laptops and IOT devices, and increasing electrification of vehicles (xEV). ATE providers must anticipate these trends, proactively developing test solutions that handle increasingly advanced requirements without compromising accuracy, speed, quality, and cost of test. This unprecedented growth is expected to drive over eight billion dollars of ATE revenue by 2028 as shown in Figure 1, driven primarily by the compute, automotive and mobile market segments.
Figure 1: ATE TAM History and Forecast and ATE Growth Drivers. Source: Teradyne
To achieve the performance improvements required for high performance computing and edge computing, the industry continues to develop chips based on smaller process nodes into the Angstrom scale. This also increases complexity as chips become smaller, more powerful, and more efficient and they require highly specialized and precise testing to identify potential defects. To meet the challenge of these smaller geometries, Teradyne’s solutions incorporate testing architectures that ensure thorough and rigorous wafer-level testing and fault detection in ultra-dense nodes. These test systems, like the UltraFLEXplus, ensure the quality and reliability of the smallest, most intricate chip designs.
Another way for advanced chips to hit the increasing performance targets is to use new packaging techniques like 2.5D/3D stacking and chiplets, in heterogeneous integrated packages. This adds a full slate of additional testing requirements and capabilities, necessary to ensure seamless operation between densely packed components like CPUs, GPUs, and memory. Teradyne supports known good die (KGD) and known good interposer (KGI) processes, assessing each chiplet functionality to prevent defects. These ATE system test capabilities ensure die-to-die interconnectivity and reliability in complex advanced heterogeneous integrated packages.
To accommodate the complexity of advanced digital chips and heterogeneous integration, a range of test strategies are in play. With FlexTest (see Figure 2), shift left and shift right test strategies ensure that test coverage is balanced across the manufacturing flow. Moving tests earlier in the development process reduces overall costs by identifying and resolving defects sooner. Conversely, shifting test coverage right extends “mission mode” testing to later stages, including post-manufacturing, ensuring that any latent defects are caught before reaching the consumer. These strategies work together to optimize yield, cost and quality.
Figure 2: FlexTest optimizes the cost of quality across test insertions in the manufacturing flow
In addition, even as chip packaging advancements match the demand for data processing, new materials may be required for next-generation data needs—specifically, silicon photonics will transform data centers by enabling high-speed, energy-efficient data transfer. To handle these new technologies, Teradyne’s testing systems address the unique requirements of photonics and electronics integration. Co-packaged optics testing is a key area where Teradyne’s ATE supports data integrity and transfer speed, ensuring these components can efficiently manage massive data flows. (See Silicon Photonics Raises New Test Challenges and Teradyne Announces Production System for Double-Sided Wafer Probe Test for Silicon Photonics)
Edge computing, which requires lower power, high-efficiency semiconductors that can process data locally for real-time applications across industries like healthcare, smart homes, and agriculture are driving a new wave of technologies. For edge computing, Teradyne’s ATE test solutions, like the UltraFLEXplus, focus on optimizing yield through increased accuracy, and test throughput, ensuring these lower-power semiconductors devices perform reliably in diverse environments. By leveraging ATE systems tailored to assess real-time test data capabilities and edge processing efficiency, the company is enabling the next wave of edge AI innovation in smartphones, laptops, and IoT devices.
The same challenge extends to the automotive arena as electric vehicles (EVs), autonomous driving (AD), and advanced driver assistance systems (ADAS) are transforming automotive technology. Increasingly complex semiconductor systems are required to ensure reliability and driver safety. For these automotive applications, Teradyne has developed high volume ATE solutions, like the ETS-88, for automotive SiC and GaN power semiconductor devices, and the UltraFLEXplus for AD/ADAS testing for 76-81 GHz radar testing.
The future of test in an evolving semiconductor landscape
Across all these new technologies and their demands on test systems, we are in an era where data also drives test processes. To capitalize on the value of test data, Teradyne offers integration with leading analytics providers through our Archimedes analytics solution to optimize production, enhancing yield while reducing costs. By applying insights from this real-time ATE data, manufacturers can improve process efficiencies and make predictive adjustments using data analytics, artificial intelligence and machine learning technologies.
Clearly, the semiconductor landscape is complex, evolving, and increasingly advanced in its design and manufacturing methodologies. As semiconductor testing becomes more sophisticated, it’s crucial that ATE leaders help foster a seamless ecosystem of tools, processes, and standards. With this rapid pace of technological change, ATE companies need adaptable test platforms that can evolve with new standards in data transmission, automotive safety, and AI processing. This adaptability will enable them to offer long-term value to semiconductor manufacturers globally.
For instance, Teradyne’s engagement in initiatives like SEMI’s Smart Data & AI Initiative reflects its commitment to data sharing across manufacturing stages – improving yield and quality through open, interoperable standards. By proactively supporting industry collaboration, the company is paving the way for a unified and resilient semiconductor ecosystem.
To further ensure the industry’s future, Teradyne actively collaborates with educational institutions to prepare the next generation of engineers. By investing in skills development and providing access to advanced test technologies, the company supports the industry’s long-term need for skilled talent.
In summary, the next generation of semiconductor technology presents both challenges and opportunities for ATE. Test requirements are refined with each innovation in data centers, edge computing, automotive applications, and more— driving a flexible, adaptive approach to ensure that ATE solutions continue to meet evolving needs. Teradyne is at the forefront of this effort, building the foundations of tomorrow’s test ecosystem, and dedicated to supporting industry growth with solutions that balance efficiency, quality, and sustainability.
Dr. Jeorge S. Hurtarte is currently Senior Director of SoC Product Strategy in the Semiconductor Test division at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. Jeorge is on the Advisory Board of SEMI North America and serves as co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Chapter. Jeorge holds a PhD in Electrical Engineering, and master’s degrees in business administration, computer science, and telecommunications. He is a visiting professor at the University of California, Santa Cruz and the University of Phoenix, and is the co-author of the book Understanding Fabless IC Technology.