The Titan System Level Test (SLT) platform delivers maximum flexibility, scalability and density in semiconductor test environments that require the highest levels of system performance testing.  Its asynchronous slot architecture offers unmatched utilization and lower cost of test across a large mix of products while providing a 30% throughput advantage over traditional batch systems.

Other benefits of the Titan SLT platform include: 

  • High Operational Efficiency 
    • Delivers high factory floor density as a result of its small footprint
    • Offers the ability to test two different products at the same time
    • Provides an automated product change-over process resulting in minimal product change-over time
    •  Enables maintenance to be performed without stopping system operation
  • Production proven solution for PoP Testing
    • Ensures high placement accuracy through the use of a vision system
    • Maintains high signal integrity using ATE style interconnects
  • Flexible and Modular Architecture
    •    Integrates existing customer test HW/ SW
    •    Enables faster ramp to production

The flexible Titan architecture enables customers to integrate existing hardware into Titan’s functional rack, slot and/or carrier.  This reuse of hardware and software allows for test program commonality, faster deployment of programs, and efficient program support.

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  • Changeover Kits

          • Titan’s architecture enables significant device transition flexibility at low changeover time and cost
          • Minimal Teradyne or customer developed components are required for each device type change:
                   • Socket Lids (Teradyne)
                   • DUT shuttles (Teradyne)
                   • Updated device specific vision job (Teradyne)
                   • Test board and socket (Customer or Teradyne)

  • Rack Baseline Configuration

          • Up to 320 sites (160 slots) per system
          • Slots are fully asynchronous for both load and test
          • Offers 15°C air cooling for testing of up to 50W device power DUTs
          • Up to 15 fail bins available
          • Slot pairs can be serviced while the system continues operating

          • 1Gbps Ethernet port per test computer
          • 1 USB 3.1 Gen 2 port per DUT
          • 1 Serial port per DUT (SPEW debug)
          • 1 JTAG enabled port to each DUT
          • 1 SPI interface to each Test Board
          • Sustained DUT + Test Board Power: 10W per site
          • Configurable voltage: 3.4V – 10V
          • Power control/measurement
          • Voltage margining +/-10%