The recent trend in the industry has been a shift towards the construction of systems by integrating multiple chiplets into a single package. This paper explores the application of the Tessent Streaming Scan Network (SSN), a revolutionary approach to scan testing, in the context of Multi-Die Chiplet Packaging. SSN facilitates concurrent testing of cores using a reduced number of scan pins, thereby decreasing both test time and scan data volume.

The study focuses on a case where the customer has begun to implement SSN on the CPU die of their new device, while retaining traditional scan testing for the DDR and PCIE dies. This scenario presents several challenges, including channel assignment for multiple time domains (where different Dies run concurrently for the scan test), scan vector memory calculation, and balancing scan bit allocation across instruments. The hardware design also requires careful consideration, particularly when the SSN is operating at higher speeds (300MHz). Factors such as trace length, trace width, and 50-ohm termination need to be managed effectively. The paper will further demonstrate the potential for optimizing vector memory through functional vector compression (flexible scan pins). Finally, it will discuss the process for printing out the SSN sticky bit status in the event of failure occurrences. This paper aims to provide valuable insights into the practical application and optimization of SSN in the context of Multi-Die Chiplet Packaging.