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  • Instrument Overview
    • Teradyne PXI Express HSSub instruments address the challenge of recent and upcoming test requirements including increasing speed, data volume, protocol and processing complexity, as well as low-latency UUT interaction
    • Instruments are configured and accessed via application-specific HSSub Apps that are authored by Teradyne, end users, or third-party developers
    • HSSub Instruments employ a Three-Tier architecture to perform the critical operations associated with old, new, custom, and standard digital interfaces
    • The time-critical operations take place within the instruments, independent of the central computer and Windows operating system
    • Multiple autonomous instruments, independent of central resources, support concurrent asynchronous UUT interfacesHSSub-Three-Tier-Architecture.PNG

    There is a wide range of HSSub instrumentation that provide tier1, tier 2, or combined functionality.

  • Reconfigurable Core Instruments
    • HSSub 5010HSSub Core Instruments combine a Test Defined FPGA for low-level I/O Bus Processing (tier 1) and a multi-core processor with RTOS for Upper Level Protocol Real-Time Processing (tier 2) into a single open-architecture instrument
    • Two Core Instruments share identical internal structure:
      • The Serial Core Instrument supports up to 16 bidirectional channels at up to 3.125 Gb/s
      • The LVDS Core Instrument supports up to 72 LVDS differential pairs at up to 800 Mb/s
    • A TPS-invoked HSSub App loads processor-based procedures and Test Defined FPGA code, configuring the instrument in seconds
    • The processor and FPGA have large, high-speed local memories
    • Each instrument can run autonomously, independent of the Windows-based computer (tier 3), and multiple instruments can run concurrently
    • Direct paths between tiers 1 & 2 provide the lowest possible latency for time-critical protocols
    • For more information on Core Instruments:
  • Real-Time Processing Modules
    • HSSub 5020The Real-Time Processor Module provides the same multi-core processor with RTOS capability as the Core Instruments
    • The module typically provides Real-Time Processing (tier 2) support in conjunction with other  HSSub instruments handling low-level I/O Bus Processing (tier 1)
    • HSSub Apps associate the processor modules with other instruments and configures them within seconds
    • Each Real-Time Processor Module and associated instruments can run autonomously, independent of the Windows-based computer (tier 3), and multiple groups of instruments can run concurrently
    • For more information on Real-Time Processor Module:
  • Reconfigurable IO Expansion Instruments
    • HSSub-Reconfigurable-IO-Expansion-Instruments.pngHSSub Reconfigurable IO Expansion Instruments provide low-level I/O Bus Processing (tier 1) with large, high-performance Test Defined FPGAs
    • Reconfigurable instruments can be repurposed from one TPS to another to meet a wide range of bus requirements; standard-compliant as well as variations from standards, well-specified as well as those with evolving needs
    • A TPS-invoked HSSub App loads the Test Defined FPGA code, configuring the instrument in seconds
    • Each instrument contains large, high-speed local memory directly accessible to the FPGA
    • IO Expansion Instruments may be controlled directly by the tier 3 Windows computer for applications that do not require real-time support
    • IO Expansion Instruments may be associated with a Real-Time Processor in a Core Instrument, or a standalone Real-Time Processor Module
    • Each IO Expansion Instrument has unique capabilities to support applications with various I/O signal requirements, channel counts, and parallel or serial buses
    • For more information on Reconfigurable IO Expansion Instruments:
        LVTTL TTL  LVDS  Serial
       HSSub-6020 LVTTL
       X    X  
       HSSub-6040      X  5 Gb/s
       eDigital-6020A  X  X  X  
       eDigital-6020C  X X  X  
       HSSub-6100 12G Serial       12.5 Gb/s
  • Flexible IO Expansion Instruments
    • HSSub 9010Flexible IO Expansion Instruments share a common, high-performance FPGA-based infrastructure
    • Integrated Physical Interface Modules (PIM) provide bus-specific I/O capability
    • A TPS-invoked HSSub App loads the Test Defined FPGA code, configuring the instrument in seconds
    • Each instrument contains large, high-speed local memory directly accessible to the FPGA
    • IO Expansion Instruments may be controlled directly by the tier 3 Windows computer for applications that do not require real-time support
    • IO Expansion Instruments may be associated with a Real-Time Processor in a Core Instrument, or a standalone Real-Time Processor Module
    • Standard Teradyne-supplied HSSub Apps and utilities provide the most commonly required functionality
    • For more information on Flexible IO Expansion Instruments:
      1G Ethernet RS232/IRIG-B  RS485  HOTLink/ECL
    Bus Controller
     Dedicated Chipset FPGA FPGA Dedicated HOTLink FPGA ECL
     HSSub-9030      X  X
     HSSub-9050  X  X  
  • Standard Bus Instruments

    Dedicated-Standard-Bus-Instruments_Family-Shot.png

    • The HSSub dedicated bus instruments provide the highest density and performance available in single-slot, 3U PXI Express form factor
    • The most widely used standard serial buses are best served by instruments based on bus-specific dedicated chipsets with provide a broad range of configurability that is controlled by HSSub Apps
    • HSSub-6090/6091 Ethernet instruments:
      • Support copper-based or optical Ethernet
      • Share data with Tier 2 functionality if real-time Upper Level Protocol processing is required
    • The HSSub-6120 FireWire Instrument implements the AS5643 Upper Level Protocol in an onboard Tier 2 Real-Time Processor
    • The HSSub-8030 provides common PC buses in an instrument as a more supportable approach than servicing the UUT directly from a computer
    • For more information on the Standard Bus Instruments:
  • Additional Instruments & Accessories

    Additional-Instruments---Accessories_Family-Shot.png

  • Overview
    • Teradyne-Defense Aerospace-High Speed SubsystemThe Teradyne PXI Express-based High Speed Subsystem (HSSub) addresses defense and aerospace ATE requirements that are common to most recent designs:
      • Buses with increasing speeds and protocol complexity
      • Increasing data handling and processing demands
      • Need for lower latency interactions with the unit under test
      • Integrated support of the latest buses as well as legacy interfaces
    • HSSub is scalable to address the full range of ATE integration:
      • HSSub can consist of a single instrument or multi-chassis solution
      • HSSub integrates into existing or new systems
      • HSSub instruments can be mixed with PXI and PXI Express instruments from other vendors
      • HSSub solutions address large-scale ATE as well as desktop test requirements
    • HSSub provides the most economical approach for developing and sustaining test capability for the range of test problems facing engineers today.
  • Applications
    • Commercial solution for defense and aerospace applications that demand both performance and long term support
    • App-based application solutions simplify TPS development and deployment, as well as adapting to changing requirements
    • Solutions for speed, protocol complexity, and flexibility that are beyond the capability of current system instrumentation
    • Emulation and replacement of obsolete equipment in a well-supported, sustainable platform
  • Advantages
    • Replaces multiple single-purpose instruments and complex custom test adapter circuitry
    • Proven Teradyne product longevity and support infrastructure provides the lowest long-term logistics cost
    • High performance, flexible App-based architecture results in the lowest development costs and the highest production throughput
  • HSSub Three-Tier Architecture
    • The unique HSSub Three Tier Architecture addresses the ongoing increase in critical upper-level operations such as video, communication and control protocols, data management and processing that must take place as tests execute.
    • Each of the Three Tiers serves a specific role in addressing digital interface requirements:
      • The Tier 1 I/O Bus Processing addresses low-level standard, custom, legacy, and future bus requirements using a combination of instruments with rapidly reconfigurable FPGAs or the highest performance dedicated chipsets.
      • The Tier 2 Real-Time Computing addresses Upper Level Protocol requirements, with emphasis on low-latency, high-throughput test operations, performed by real-time processors and reconfigurable FPGAs.
      • The Tier 3 PC-Based Resource Management provides the TPS with open, standards-compliant infrastructure software for setup, coordination, and supervision of the multiple autonomous instruments
    • The programming of real-time processors and reconfigurable Test Defined FPGAs” is open to all, and encapsulated within HSSub Apps
  • HSSub Apps
    • HSSub-Apps-Diagram_250x319.pngHSSub Apps provide the TPS developer with high-level solutions without the burden of dealing with unnecessary low-level details
    • HSSub Apps configure the instruments and provide the TPS with a programming interface
      • Loads FPGAs and configures chipsets (tier 1)
      • Loads RT Processor code (tier 2)
      • Provides IVI-like C-language API (tier 3)
      • Provides application-specific test logic above the bus interface tier
    • Most TPS developers do not need to create HSSub Apps
    • Unlike conventional single-driver instruments, HSSub instruments can be associated with multiple HSSub Apps:
      • For various combinations of low-level buses and Upper Level Protocols
      • For version flexibility and reduction of regression testing with frozen HSSub Apps for released TPSs, and new versions  for additional requirements
    • HSSub App development is totally open and is used by Teradyne, third-parties, and end users
    • Single-file HSSub Apps simplify distribution, deployment, and revision control
  • HSSub TriFlex Infrastructure Software
    • The HSSub TriFlex software integrates the three tiers to optimize flexibility, high performance, and ease of TPS and HSSub App programming
    • TriFlex software is include with all Teradyne-supplied foundations and individual HSSub instruments
    • On the HSSub Windows computer, TriFlex services provide consistent management of the underlying instruments and a library of common tasks to simplify TPS development
    • TriFlex supports the leading industry-supplied and government-approved tools from Microsoft, National Instruments, Wind River, Xilinx, MathWorks, and others
    • Where HSSub App development is required, TriFlex simplifies the effort through critical interfaces at each tier:
      • Tier 3 PC-based drivers that communicate with the instruments, and support the HSSub App interface to the TPS
      • Tier 2 Real-Time Processor interfaces connect to the tier 3 PC driver, the tier 1 low-level hardware, and provides a library of common test functions
      • Low-level Tier 1 hardware is accessible by interfaces on both the tier 3 PC and tier 2 RT Processors
      • Development for instruments with reconfigurable FPGAs is simplified by template code based on standard design patterns, and TriFlex interfaces provide access
      • Instruments with dedicated tier 1 chipsets are highly configurable, directly supported by the TriFlex software interfaces
  • Configurations

    HSSub-Confirgurations-Shot.png

    • HSSub is highly scalable, with soutions ranging from single instruments to  complete test systems, for use on the desktop or as a component in large-scale ATE
    • HSSub configurations are based on a standard PXI Expess chassis, which is known as a Foundation when combined with HSSub instruments, a controlling computer, and the HSSub TriFlex Infrastructure Software
    • Teradyne supplies fully-integrated HSSub Foundations of all sizes for use in existing or new test systems
    • An HSSub instrument with the included TriFlex software can be integrated into a user’s existing chassis in place of a Teradyne-supplied Foundation
    • Teradyne Foundations offer a variety of mechanical interfaced alternatives including Virginia Panel mass interconnect approaches supporting both cabled and ITA assemblies
  • Instrument Interface Approaches
    • Instrument-Interconnect-Options.pngDirect-to-instrument interfacing
      • All instruments employ high-density, high-performance front panel connectors
      • Cables for system integration can be designed and fabricated by Teradyne, end users, or third parties
      • Best alternative for integrating into existing systems with a suitable UUT interface
    • Mass Interconnect
      • HSSub instruments are available with Teradyne-designed funnels and receiver modules that provide the best combination of performance, density, flexibility, and high insertion count
      • Receiver modules accept both Virginia Panel G20 ITAs and i2 MX cabled connections
    • Teradyne can design and supply HSSub with special interfaces such as MIL-38999 and optical I/O
      • Interface compatibility when replacing legacy capabilities
      • Application-specific mechanical requirements
  • Optical I/O
    • Optical-I-O-2.pngHSSub provides extensive support for fiber optic UUT interconnects which are displacing copper cabling in many new designs, typically for serial interfaces operating at 1 Gb/s and above
    • Serial Core Instrument with Optical IO Expansion Instrument
    • 1G Ethernet
    • 10G Ethernet
      • The HSSub-6091 10G Ethernet Instrument provides four integrated SFP+ pluggable transceiver cages with direct optical support without external conversion
      • Supports 10GBASE-SR (LAN) and 10GBASE-SW (WAN) 10G optical Ethernet
      • Supports 1000BASE-SX 1G optical Ethernet
    • 12G Serial IO Expansion Instrument
      • The HSSub-6100 12G Serial IO Expansion Instrument provides eight ports in four integrated SFP+ and one QSFP+ pluggable transceiver cages with direct optical support without external conversion
      • Reconfigurable FPGA support for multiple low-level protocols to 12.5 Gb/s
  • Foundations
    • HSSub-Foundations.pngHSSub Foundations consist of:
      • A commercially available PXI Express chassis
      • A server-grade computer running 64-bit Microsoft Windows OS
        • Internal to the PXI Express chassis
        • External computer interfaced via PXI MXI-Express (PCIe)
      • Teradyne HSSub TriFlex Infrastructure Software, available with: Teradyne-supplied Foundations
      • Teradyne HSSub instruments
    • HSSub supports commercially available PXI Express chassis
      • Small chassis supporting as few as three instruments
      • Full-size chassis supporting up to 16 instruments
      • Multiple chassis interconnected with high-bandwidth, low-latency PCIe technology
    • Fully integrated systems – Spectrum HS
      • Fully integrated PXI/LXI-centric open-architecture system
      • Built around a HSSub Foundation core