With the size of semiconductor transistors decreasing and chip complexity increasing exponentially, semiconductor test has become essential to ensuring that only high-quality products go to market. With the introduction of more rigorous acceptable quality level (AQL) certifications, test methods must constantly evolve to meet these standards, and system level test (SLT) and traditional test using automated test equipment (ATE) deliver a comprehensive test strategy to ensure devices exceed quality requirements.
System level test (SLT), which can identify and solve a number of test problems, is not new technology. It’s been used in the computing field since the late 1990s. However, with the exponential growth of transistors integrated into the chip, the complexity of the chip is increasing, and more integrated chip (IC) manufacturers are using SLT to improve the yield and quality of their chips.
What Is System Level Test and Why Is It Different?
System level test, also known as functional test, is a method of testing the device under test (DUT) in its end use. By running the operating system and using the device under test to perform general or targeted application tests, additional verification can be accomplished beyond that of traditional ATE testing. SLT tests are typically normal device operations with additional verification steps.
Industry trends driving System Level Test
In the past 20 years, the SLT market has grown considerably due to several trends in the chip industry.
First, device quality requirements are increasing. In the past 10 years, people have become more dependent on mobile phones and other electronic devices, resulting in increasingly high requirements for the quality of chips. This has driven manufacturers to conduct comprehensive tests for their chips and systems to reduce the possibility of problems encountered by end users after purchasing products. Because of this, SLT for mobile devices has experienced rapid growth.
Another trend is in the automotive field. In assisted autonomous vehicles, electronic devices and software are used to sense and respond to events with automatic steering or braking. Advanced driver assistance systems (ADAS) require higher standards, which means that the performance of ultra-high-power and mixed signal devices, as well as platform efficiency and thermal stability is critical.
Chip suppliers continue to drive technology to the limit to improve performance, battery runtime and yield, which means they must:
- Deliver products from new process nodes as early as possible, although the process fault rate may be high
- Operate at a voltage as low as possible to extend the battery runtime
- Fine tune the phase-locked loop (PLL) setting to maximize yield
- Adopt cutting-edge packaging technology to improve transistor density and performance
Additionally in the automotive infotainment sector, automobile companies are closer to the forefront of technology than ever before. Adopting cutting-edge technology to achieve higher stability enables them to shorten the time to market for automotive infotainment products.
Another growth area for SLT is in big data processing, and edge and cloud artificial intelligence (AI) applications, with their requirements for high power – from hundreds to thousands of watts.
Given the variety of requirements driving these diverse markets, it has become critical but also very complex to ensure high-quality components are shipped in finished products. As the technology is constantly pushed to its limits, the use of SLT has become ever more important in preventing faults from being missed and ensuring that components reach the required quality levels. In addition to improving product quality, running the equipment as close to the terminal application as possible assists in shortening the time to market.
Traditional Test Coverage Becomes More Challenging
IC manufacturers are constantly integrating more functions into a single chip. Take mobile processors as an example. In the early days, functionality was limited primarily to phone calls. Today, mobile devices support graphics, image processing, advanced security and more. In the past, communications were accomplished via digital processing but today’s devices include voice and biometric data processing, and even AI algorithms. Because of this, the application processor (AP) needs to be integrated with the high-speed memory.
Processors are evolving over time and the features they deliver are expanding rapidly. Features like tracking health metrics, recording and storage, connection and control, communications with peripheral car sensors to ensure safety, and simplifying people’s lives through machine learning and AI are increasing productivity and safety all the time. Faults associated with the interaction of these functional blocks may be particularly difficult to capture, especially when the test interfaces within them use different languages.
All of these new functions are integrated into one AP, which means increased transistor count that in some cases outpaces Moore’s Law.
Of course, test challenges go beyond the device functions. When we integrate multiple transistors into the IC, trade-offs must sometimes be made, leading to the loss of test coverage achieved via traditional methods. With this increase in transistor count, the probability of faults is higher and additional tests are needed to avoid an increased fault rate. ATE test is no longer sufficient to catch all faults and so SLT can be used to achieve more comprehensive test coverage.
How to Run SLT?
SLT is a functional test of a product in a manner closely matching its end use. The “system” part is implemented on a custom system level test board and the test flow includes:
- Performing specific operations: running the device’s general functions and target applications inherent in the system and verifying they work as expected. These operations can include starting chips, loading the operating system, or running specific programs written by a module, such as performance evaluation programs. The system level test board used is similar to the reference design or evaluation board provided to the customer.
- Determining if the operation was successful: measured according to the test results or the success/failure of the operation. For example, when verifying whether an internal process is successfully executed, the operating system is validated to confirm it can be successfully started or a specific value is measured (e.g., a comparison between the performance test result and the threshold value) as the basis for judgment.
In most cases, the system in SLT is equipped with on-board processors to execute the test flow. Since SLT mainly focuses on the system on a chip (SoC) and system in package (SiP) chips, the test processor is usually a part of the device under test. If this is not the case, the peripheral test system of the device under test will need to be equipped with a suitable processor.
The SLT board circuit around the device under test may change according to the requirements. A fault escape report can quickly and easily be displayed on screen. This type of test is difficult to achieve on ATE because a significant amount of fault analysis must be carried out to trace the functional fault to the transistor level. SLT is better suited for this type of test because it can use the exact use case that triggers the fault, and quickly add this functional test to the SLT test, which can almost immediately identify the root cause of the fault escape.
However, since SLT is a functional test that simulates the real terminal use scenario, rather than the structural tests we see in ATE, SLT test time is typically longer than that of traditional ATE. As such, parallel test efficiency becomes important to maintaining the cost-effectiveness of SLT. ATE test time is typically based on a unit of 10 seconds, while SLT test time is based on a unit of one to ten minutes. To achieve the highest efficiency, parallel testing must be an order of magnitude higher than ATE.
In the final analysis, cost matters. A comprehensive test strategy ensures faults are captured as early as possible, avoiding downstream process costs. ATE wafer test performs well in capturing faults early in the process, including transistor level problems, sensitivity to changing frequency/voltage levels, and compliance with basic design specifications.
Some faults are generated in the packaging process, and ATE final test is used to identify these issues. However, there are still some faults that are so subtle and complex that the device will never pass the test acceptance process if a low defective parts per million (DPPM) level is required.
For conventional quality requirements, ATE costs typically increase as test time increases. This increase is generally controllable and, to some extent, linear. However, when a high complexity transistor out is required, the cost of ATE will eventually reach an inflection point in the curve and grow exponentially.
This is mainly because it takes a lot of time to identify these faults, and they need to be tested with peripheral devices. Some of these tests are completed on ATE today, including some parameter and functional tests. However, in some cases, the number of extra circuits and the length of the test means this type of test is not viable on ATE. It is interesting to note that the SLT cost/test time does not increase with the increase in complexity because it is only starting or running an application. Over the past 50 years, ATE has been very good at capturing transistor level design parameter faults and will continue to be the most cost-effective way to do so. SLT should be used for tests that cannot be implemented on ATE using real-world chip application scenarios.
Why are the faults of many classes captured in ATE but not SLT? The reason is that, unlike ATE, SLT does not systematically test every transistor and its parameters, but only tests a subset of real-world applications in the device and delivers functional results. It is almost impossible to run every conceivable application program to excite every transistor and generate faults.
The cost-effectiveness of SLT is achieved by using it to find a reasonable percentage of faults that are caused by issues that ATE cannot test or by simultaneously stimulating the chip and multiple IP modules around it. The cost of test for each device could be one quarter or less compared to ATE due to the concurrent testability (the number of devices tested at one time) being much higher.
With complexity continuing to increase exponentially and the number of mission critical applications continuing to rise, combining ATE and SLT test is an ideal solution for maintaining high quality levels at the lowest cost.
To some extent, ATE cost is linearly related to complexity/transistor count and so it should be used to catch faults at the wafer and IC level. SLT is very cost-effective at screening out the last few, difficult to find faults at the end of the test flow. Therefore, adding SLT to the end of the existing ATE test flow is often the most cost-effective strategy for mission-critical applications with very high quality requirements.
Only through the use of both ATE and SLT test can a comprehensive test strategy be achieved. By considering a number of factors, including the required quality level and costs, companies can determine the best balance between ATE and SLT.
One of the advantages of the Teradyne Titan™ SLT tester is true parallel test. Each chip is completely independent of its adjacent chips, which is a more effective way to perform SLT and batch processing.
In addition, Teradyne has a large-scale automated production platform that has been in use for more than ten years. By combining our storage automation architecture with our semiconductor test expertise, Teradyne Titan delivers a comprehensive SLT automation and test solution.
SLT is a supplementary test step and an extension to ATE test to ensure the required quality levels are met. Teradyne provides solutions that support the entire test lifecycle, ensuring our customers can achieve maximum test coverage to deliver the highest quality products to market while reducing test time and cost.
SLT has existed for nearly 30 years and is mainly used for cutting-edge, large-scale digital computing applications. Some faults can only be seen in real application scenarios and SLT is uniquely suited for this. It is an application-level test of chips on system level test boards using dedicated peripherals to capture the last 0.00xx% of faults and achieve the lowest possible error escape rate.
The growth of SLT is due to the increasing demand for quality, the rapid growth of electronic application scenarios, the increase in the complexity of chips, and the shorter time to market windows. By combining ATE and SLT test, Teradyne provides a comprehensive test solution for high volume manufacturing, which aims to capture the most faults and can address not only mobile phone application processors, but also processors in the automotive and high-performance computing end markets.
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Natalian Z. Der is the Director of Business Strategy and System Level Test Marketing at Teradyne. Natalian joined Teradyne in 2018, managing Teradyne’s UltraFLEXplus product and leading Teradyne’s China strategy. Prior to joining Teradyne, Natalian served as the Senior Director of Global Product Line Management at Harman, a Samsung company, for the Car Aftermarket Electronics line. Natalian started her career at Silicon Labs, where she managed broadcast RF ICs for the handset and automotive market. Natalian holds a Master’s Degree in Electrical Engineering and a Master’s Degree in Business Administration from Rice University in Houston, Texas.