AI Chiplet Architectures Redefining Test Insertions

AI drives demand for xPU [1], HBM, switches, and CPO, but lithographic limits mean monolithic dies can’t keep pace. Instead, the industry is moving to all sorts of complex packages. This creates new challenges for test. Here’s a look at how test vendors are responding.

The Challenge: From Monolithic Die to Interposer-Based Modules
With heterogeneous integration well established and supported by evolving standards, the industry is at a technical inflection point: AI accelerators are no longer constrained primarily by transistor scaling, but by integration strategy and package-level interconnect density. Compute die, HBM stacks, and I/O die are assembled on silicon interposers and, increasingly, in panel formats. This brings into focus new physical realities such as reticle limits (maximum size 26mm x 33mm), microbump pitch, TSV routing, and die-to-die interfaces.

We must recognize the impact of lithographic limits, which dictate how much can be squeezed into a particular die size, when paired with these physical realities. The result is a need for multi-chip designs using 2.5/3D integration packages to create more complex systems. Key test factors are grounded in geometry, pitch, and interconnect density – variables that directly affect probing, access, and test coverage.

Today’s industry trend integrates multiple chiplets and multiple dies. These are stacked either on top of each other like HBMs, or side by side on a silicon interposer used as an interconnect layer. This then moves into the package substrate and then into the circuit board. This complexity presents new test challenges. Once multiple, high-value die are assembled on an interposer, the package architecture itself begins to dictate where and how validation must occur. Teradyne recognizes this as a trend with growth potential for the next decade and is responding with new test solutions. See, for example, Teradyne’s recent press release where Teradyne’s UltraFLEXplus tester is paired with TEL’s Prexa SDP prober for singulated device probing.

Known-Good Everything: The Economic Imperative
High-value AI accelerator companies change test strategies and test insertion steps based on economic drivers. With the average selling price of a data center GPU rising to about $28,000 by 2030 [2], high scrap costs mean singulated die test, stack validation, and interposer module verification are not optional. Computing and networking devices must be tested, and test coverage is tied directly to yield and quality protection.
At the system level, complexity scales rapidly. A single AI data center rack can integrate hundreds of GPUs, thousands of memory devices, and multiple high-speed switches, all interconnected through dense chiplet-based architectures. Each GPU itself is no longer a monolithic device, but a heterogeneous assembly of compute die, stacked HBM, and high-speed I/O, and even photonics interconnect, creating thousands of interconnects.

This complexity is amplified by the integration of co-packaged optics (CPO), where optical engines (often deployed in arrays of dozens per system) are placed alongside compute silicon to enable high-bandwidth, low-power data movement. Because these optical engines are multi-die subsystems combining electronic and photonic components, they must be validated as known-good optical engines before integration. A single defective component can compromise the entire system. The underlying goal is supporting the shift toward “known-good everything”, with metrology, ATE (automated test equipment), and SLT (system level test) combining to form a layered quality strategy.

For example, by identifying physical defects at early stages (pre-bond and mid-assembly), metrology [3] helps prevent faulty components from being integrated into expensive multi-die packages, where failures would be far more costly. As a result, its role is expanding alongside advanced packaging, becoming an essential step in improving yield, reducing risk, and enabling more effective downstream test strategies.

Metrology focuses on physical integrity and verification: are the structures built correctly? It measures dimensions, warpage, alignment, and interconnect quality (e.g., microbumps, TSVs, spacing) and often uses optical or x-ray inspection to catch defects during and immediately after assembly steps. This happens pre-bond and mid-process, before full electrical validation. ATE, by contrast, verifies electrical and optical functionality and performance at the device or module level, ensuring the chip or package behaves as intended. Then SLT validates the device in a real or near-real operating environment, catching issues that only appear under system conditions, or “mission mode”, and validating the device works in the overall system.

Figure 1: Known-Good Everything – metrology, ATE, and SLT form a layered quality strategy. Source: Teradyne.

Module-Level Probe: A Structural Shift
There are practical implications for probing large interposer-based modules before substrate attach. This includes mechanical scale, current delivery, power dissipation, contact integrity, probe force, and thermo-mechanical warpage stability at probe. Overall, the more chips tested, the more power consumed (into thousands of watts).

More complexity and more chips also introduce possible new areas for defects. ATE structures must verify the assembly integrity of the chiplet stack, the multiple HBMs, the microbumps, the C4 bumps, and the interconnection before everything is assembled into the interposer and final package substrate.

Figure 2: Inside a CoW Module. A partially assembled multi-die system, tested on the interposer wafer before substrate attach. Source: Teradyne

CoW module probing introduces a fundamentally new class of test challenge, because the device under test is no longer a single die, but a partially assembled multi-die system on a silicon interposer. At this stage, electrical access is typically limited to C4 bump interfaces, requiring test to be performed before substrate attach using probe-based methods rather than traditional package test. These CoW modules are significantly larger than reticle-limited die—often exceeding 100mm², 150mm², or more on a side—which places new demands on probe mechanics, contact uniformity, and test cell architecture.

The probe interface must also support high-current delivery, tight thermal control, and high-speed signal integrity across thousands of fine-pitch interconnects. Ensuring known-good CoW modules requires verification of chiplet interconnects, microbump and C4 integrity, and interposer connectivity—driving the need for new prober designs, advanced DFT strategies such as IEEE 1838, and closer coupling between mechanical, thermal, electrical, and optical test domains.
Test cell architecture must adapt – today’s wafer probes are not suitable so Teradyne is working with its open ecosystem suppliers to expertly handle larger packages. In parallel, the industry is extending these architectures beyond wafer-based integration toward panel-level formats, or chip-on-panel (CoP). By moving from 300mm wafers to panel dimensions on the order of 310mm × 310mm, CoP improves space utilization and manufacturing efficiency, enabling lower cost per module for large, heterogeneous designs.

However, this shift to CoP amplifies existing test challenges. The larger form factor increases demands on handling, alignment, and probe scalability, while maintaining the same requirement for multi-stage test insertions. CoP also opens the door to alternative interposer materials, including glass and organic substrates, introducing new variables in signal integrity, thermal behavior, and defectiveness.

Together, CoW and CoP shift test from a die-centric model to a module-centric one, where physical scale, interconnect density, and system-level behavior must be validated earlier in the flow.

Figure 3: Test formats shown to scale – reticle die to CoW module to CoP panel; a single probe field covers only a fraction of the larger formats. Source: Teradyne.

Fine Pitch, Hybrid Bonding, and Access Constraints
As advanced packaging brings new test insertions, there are new test challenges related to both access power and active thermal control (for example, on-chip liquid cooling, and new approaches to thermal management). Further challenges result from CPO and integrating optics (for example, fiber alignment).
At the physical level, interconnect scaling is tightening, with bump pitches shrinking from hundreds of microns to 40–50µm microbumps, and in some cases moving toward hybrid bonding below 10µm. This significantly increases interconnect density while reducing available probe contact area, making physical access more constrained. The number of interconnects within a package can reach into the tens or even hundreds of thousands, increasing the difficulty of achieving full coverage.

These constraints are compounded by the rise of high-speed die-to-die interfaces, such as UCIe, which operate over short distances with low drive strength and are sensitive to signal integrity and electrostatic effects. As a result, test access must be brought physically closer to the device under test, thus minimizing parasitics and maintaining signal fidelity.
Access methodology therefore requires new approaches to probe architecture, interface design, and DFT to ensure that high-speed interconnects can be driven and observed across all insertion points.

For Teradyne, this directly translates into tighter integration between ATE instrumentation and the device interface. This reflects the need for higher bandwidth, lower-noise signal paths, advanced probing solutions, and test cell architectures that can maintain signal integrity at increasingly fine geometries.

Figure 4: As bump pitch shrinks from C4 bumps to hybrid bonding, interconnects per package rise into the hundreds of thousands. Source: Teradyne; pitch ranges per Yole Group (2025).

Integration Density Drives Insertion Density
In summary, the interposer on substrate advanced packaging can be on a wafer format with multiple chips. Eventually this gets singulated and placed on a substrate. Test leaders must be able to test this at all levels, from wafer level, singulated die, CoW module on interposer wafer tests, singulated CoW module tests, and final assembly.

Heterogeneous integration does not simply increase complexity but redistributes where quality must be assured. Test insertion architectures must evolve alongside package architecture and uncover failures in every step of the process.

[1] xPU refers to computing devices like GPU, CPU, TSU, DPU, LPU, etc.
[2] Yole Group, 2025
[3] Metrology in this context can refer to any inspection equipment technology, such as x-ray, optical or SAM.

Dr.Jeorge Hurtarte is currently Senior Director and Principal Marketing Strategist in the Compute Test Division at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. Jeorge is on the Advisory Board of SEMI North America and serves as co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Chapter.
Jeorge holds a PhD in Electrical Engineering, and three master’s degrees (MBA, Computer Science, and Telecommunications). He is also a visiting professor at the University of California, Santa Cruz and at the University of Phoenix. He is the co-author of the book Understanding Fabless IC Technology.