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January 24, 2022

Site to Site Variation in Parallel Test

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management.

An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level test module.

There’s also the engineering effort to manage the test cell resources.

And now with test data being managed by systems, analysis of this data enables engineering teams and factory floors to manage both the pass/fail criteria for a die/unit and the test cell components which support the multi-site testing.

What to Look for in a Multisite Test Solution

The goal is always to make it easy – low engineering effort, fast time-to-volume ramp – to implement multisite solutions across all segments.

  • Stringent guaranteed instrument specifications to remove channel to channel and tester to tester variation from impacting the test
  • Test program software programming model that is inherently multisite to make it fast and easy to change from x1 to xN
  • Efficient runtime architectures for low multisite overhead to facilitate low test engineering effort to achieve optimized multisite solutions
  • Smart device interface architecture that enables distributed tester signals and large applications area in the right location, delivering site-symmetric (copy/paste) DIB component placement, and thus trace routing across sites with very low variation

Multisite Test Trends by Segment

RF / mmWave

  • Consumer: 8-16+ sites
  • mmWave: 2-4 (probe head limited)

For RF/mmWave testing, the continued increase in test sensitivity and higher frequencies are unique challenges. Some of this is driven by continued low power in mobile applications, which relates to more accurate and sensitive device under test (DUT) Rx tests. Higher bandwidth modulation standards in connectivity relate to more accurate error vector magnitude (EVM) measurements. These more sensitive measurements mean a higher susceptibility to any channel to channel differences or interactions during the test.

For RF, one solution is to strongly shield signal paths to the DUT interface board, and have very accurate and calibration-controlled performance – the device interface board is where the care and consideration should be placed. An RF signal delivery approach which allows the cables to connect very close to each DUT site, so the work is focused on the best design for the last ~3 inches on the printed circuit board (PCB) to the probe head or socket. Instruments which support de-embed factors for this segment are necessary, but this relies on each interface to be properly characterized.

The increase in frequency, test accuracy, and number of RF signals raises challenges to ingress route traces to inner-array connections without signal degradation or interference. The importance of advanced PCB design knowledge, and even considerations for fabrication variations, is critical for success here. New factors come into play for the higher mmWave frequencies such as the proximity to metal structures (e.g., the socket).

Digital

  • MCU: ~16 to 4K
  • Advanced Digital: 1/2/4 to 16

Within the digital devices space, there are a number of different device types – from high site count microcontroller units (MCUs) and mobile processors, to leading edge advanced digital processors (xPUs, AI, Networking devices).

For advanced digital devices, mobile application processors (MAPs) still drive the highest site counts due to volume economics. Test strategies differ across the market, so site counts range from 6 to 16 sites currently.

The latest high performance compute devices drive very high power transients during test (typically scan tests). These are big devices, sometimes starting at x1, but pushing into 2-4 site testing. The key multisite challenges today are consistent high quality power delivery, and correspondingly the ability to control the temperature across sites.

Vmin trimming for power efficiency is a key test for both mobile and data center applications. Any variation across sites of the critical core power supply can result in millivolts of difference, which is significant for the resulting device power efficiency, as well as for test yields. Ensuring site to site consistency is key for the placement of device interface board (DIB) bypass capacitors and the related low-impedance force/return trace routing. On Teradyne’s UltraFLEXplus, the Broadside Applications Interface ensures the large PCB area for DIB circuitry is placed between the instrument connections and the DUT (as compared to pushed off to the sides of the PCB), which truly does enable site to site copy/paste placement, and resulting layout consistency. This simplicity will save test engineers DIB design time but even more importantly, it avoids the risk of longer debug times for multisite issues – or at worse, having to re-spin a DIB due to a site to site design issue.

The continued increase in scan data volumes (and resulting test times) is driving a shift to high speed serial scan approaches. This will create a renewed focus on signal quality thru the entire signal path to the DUT, into 5 to 16Gbps. Signal quality differences across sites could lead to test time impacts for pattern retries, or worse impact the test yield. Having the best instrument signal quality combined with site-consistent interfaces will be key here. As well, the automatic test equipment (ATE) systems need to adapt to manage higher data bandwidths and preserve multisite throughput efficiency, as follows:

MCUs have somewhat different considerations:

  • Smart Card devices are really pushing to extreme site counts, with recent success up to 4K sites at wafer probe.
    • Big probe heads for this many sites raise challenges of temperature variation across the chuck, which could impact device temperature sensor measurements if not managed.
    • Site to site correlation at these high counts has to be done more statistically, relying on a higher volume of data as compared to stepping a site location to a single die.
  • Secure Transaction devices are driving a significant increase in the amount of site-unique data that has to be provided to each device site. This can increase test program complexity – communicating with servers for keys, encrypting large amounts of data, and doing so with efficient test time.
  • Standard MCUs range in site counts, often higher in wafer probe (up to x64) and from ~16 to 128 for package test (and up to x320 strip test in a recent example). This is a high-mix market, so the ROI for higher multisite does not always justify the added interface costs, except for when they become high volume.
  • A unique multisite factor for MCUs is response timing variation, often related to the Embedded Flash. Generally it is a balance of multisite economics with the effort to manage site-unique timing and data.

Automotive / Power

  • Wafer Sort (WS): up to x32
  • Functional Test (FT): 8-12 for larger devices, x32 for smaller pin count
16-site wafer solution for power discrete devices

Automotive multisite test solutions combine the challenges of significantly large DIB circuit area needs, with increasing power and more accurate tests, and the overriding highest quality gates for end-market safety factors.

High current testing of complex analog ICs are particularly susceptible to multisite interactions due to improper management of return currents. The key to minimizing the DIB design challenge is having true floating instruments with a dedicated “low-force” signal path. The growth of GaN and SiC technologies raises the voltage and current transients, which will continue to increase this challenge.

Some other key tests are more sensitive to layout variations, such as leakage, delta-leakage, Iddq, and timing tests. Delta-leakage, tested before and after stress, is a key quality test where high accuracy is vital. Any layout mistakes could result in site-serialized testing (with significant 100s of milliseconds impact on each test), or the cost and time to re-spin and production-release the PCB.

Another key test is RDSon. The latest advanced voltage regulators require accurate measurements of 20mV levels under 40-100A loads. Any small site to site interaction could impact this sensitive test.

Modern battery management systems (BMS) for electric vehicles are pushing the accuracy requirements of ATE systems to levels never seen before in high channel count, high site count applications. The key to providing economical solutions to these devices is providing stimulus to the DUT with high guaranteed accuracy, and low noise in the presence of high common mode voltages.

The floating instrument architectures and DIB interface with the largest applications area as on Teradyne’s ETS systems enable best practice implementations, consistently across multiple sites.

Summary

In summary, the economic motivation for higher multisite test still holds. The same type of multisite challenges exist as they have in recent generations and continue to grow into the next degrees of technical complexity. Most of the challenges are in the device interface area, from the tester instrument DIB connection through to the device connections. While the specific interface challenges are unique across device segments, they all tend to require test engineers to extend their knowledge and expertise further into the PCB layout arena. The best test systems will take care of all the other multisite factors, and make it fast and easy to implement high multisite test solutions.

Enabling high multisite test is driving a number of design factors , from system architecture, instrument hardware and software, and increasingly in the device interface area. It is core to Teradyne’s mission and has applications across our entire product portfolio, from ATE to SLT systems.

Learn more about Teradyne’s test solutions for Advanced Compute, Automotive, Wireless and System Level Test applications or contact us.

About the Author

Ed Seng is the Strategic Marketing Manager for Advanced Digital at Teradyne. With over 20 years experience in engineering, applications, and marketing roles, he has developed test solutions for leading edge SoCs, and high speed digital and serial interfaces. He has also guided product direction for software, instrumentation, and new ATE platforms. In his current role, Ed manages the ATE roadmap for Teradyne’s digital product line. He holds a Bachelors of Science degree in Electrical Engineering from Penn State University.

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